2 * Copyright(c) 2013 Intel Corporation.
4 * Adrian Burns (adrian.burns@intel.com)
5 * Thomas Faust (thomas.faust@intel.com)
6 * Ivan De Cesaris (ivan.de.cesaris@intel.com)
7 * Julien Carreno (julien.carreno@intel.com)
8 * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 * Contact Information:
29 * This is the interface to the x86 32 bit memory and breakpoint operations.
32 #ifndef X86_32_COMMON_H
33 #define X86_32_COMMON_H
35 #include <jtag/jtag.h>
36 #include <helper/command.h>
38 extern const struct command_registration x86_32_command_handlers
[];
40 /* for memory access */
45 #define EFLAGS_TF 0x00000100 /* Trap Flag */
46 #define EFLAGS_IF 0x00000200 /* Interrupt Flag */
47 #define EFLAGS_RF 0x00010000 /* Resume Flag */
48 #define EFLAGS_VM86 0x00020000 /* Virtual 8086 Mode */
50 #define CSAR_DPL 0x00006000
51 #define CSAR_D 0x00400000
52 #define SSAR_DPL 0x00006000
54 #define CR0_PE 0x00000001 /* Protected Mode Enable */
55 #define CR0_NW 0x20000000 /* Non Write-Through */
56 #define CR0_CD 0x40000000 /* Cache Disable */
57 #define CR0_PG 0x80000000 /* Paging Enable */
59 /* TODO - move back to PM specific file */
60 #define PM_DR6 0xFFFF0FF0
62 #define DR6_BRKDETECT_0 0x00000001 /* B0 through B3 */
63 #define DR6_BRKDETECT_1 0x00000002 /* breakpoint condition detected */
64 #define DR6_BRKDETECT_2 0x00000004
65 #define DR6_BRKDETECT_3 0x00000008
68 /* general purpose registers */
77 /* instruction pointer & flags */
81 /* segment registers */
89 /* floating point unit registers */
107 /* control registers */
113 /* debug registers */
121 /* descriptor tables */
134 /* segment registers */
161 #define X86_32_COMMON_MAGIC 0x86328632
164 /* memory read/write */
190 /* lakemont1 core shadow ram access opcodes */
197 struct swbp_mem_patch
{
199 uint32_t swbp_unique_id
;
201 struct swbp_mem_patch
*next
;
204 /* TODO - probemode specific - consider removing */
205 #define NUM_PM_REGS 18 /* regs used in save/restore */
207 struct x86_32_common
{
208 uint32_t common_magic
;
210 struct reg_cache
*cache
;
211 struct jtag_tap
*curr_tap
;
215 /* pm_regs are for probemode save/restore state */
216 uint32_t pm_regs
[NUM_PM_REGS
];
218 /* working area for fastdata access */
219 struct working_area
*fast_data_area
;
222 struct x86_32_dbg_reg
*hw_break_list
;
223 struct swbp_mem_patch
*swbbp_mem_patch_list
;
225 /* core probemode implementation dependent functions */
226 uint8_t (*get_num_user_regs
)(struct target
*t
);
227 bool (*is_paging_enabled
)(struct target
*t
);
228 int (*disable_paging
)(struct target
*t
);
229 int (*enable_paging
)(struct target
*t
);
230 bool (*sw_bpts_supported
)(struct target
*t
);
231 int (*transaction_status
)(struct target
*t
);
232 int (*submit_instruction
)(struct target
*t
, int num
);
233 int (*read_hw_reg
)(struct target
*t
, int reg
, uint32_t *regval
, uint8_t cache
);
234 int (*write_hw_reg
)(struct target
*t
, int reg
,
235 uint32_t regval
, uint8_t cache
);
237 /* register cache to processor synchronization */
238 int (*read_hw_reg_to_cache
)(struct target
*target
, int num
);
239 int (*write_hw_reg_from_cache
)(struct target
*target
, int num
);
242 static inline struct x86_32_common
*
243 target_to_x86_32(struct target
*target
)
245 return target
->arch_info
;
247 bool check_not_halted(const struct target
*t
);
249 /* breakpoint defines */
250 #define MAX_DEBUG_REGS 4
251 #define SW_BP_OPCODE 0xf1
252 #define MAX_SW_BPTS 20
254 struct x86_32_dbg_reg
{
259 #define DR7_G_ENABLE_SHIFT 1
260 #define DR7_ENABLE_SIZE 2 /* 2 bits per debug reg */
261 #define DR7_RW_SHIFT 16
262 #define DR7_LENGTH_SHIFT 18
263 #define DR7_RW_LEN_SIZE 4
264 #define DR7_BP_EXECUTE 0 /* 00 - only on instruction execution*/
265 #define DR7_BP_WRITE 1 /* 01 - only on data writes */
266 /*#define DR7_RW_IORW 2 UNSUPPORTED 10 - an I/O read and I/O write */
267 #define DR7_BP_READWRITE 3 /* on data read or data write */
268 #define DR7_BP_LENGTH_1 0 /* 00 - 1 byte length */
269 #define DR7_BP_LENGTH_2 1 /* 01 - 2 byte length */
270 #define DR7_BP_LENGTH_4 3 /* 11 - 4 byte length */
272 #define DR7_GLOBAL_ENABLE(val, regnum) \
273 (val |= (1 << (DR7_G_ENABLE_SHIFT + (DR7_ENABLE_SIZE * (regnum)))))
275 #define DR7_GLOBAL_DISABLE(val, regnum) \
276 (val &= ~(3 << (DR7_ENABLE_SIZE * (regnum))))
278 #define DR7_BP_FREE(val, regnum) \
279 ((val & (3 << (DR7_ENABLE_SIZE * (regnum)))) == 0)
281 #define DR7_RESET_RWLEN_BITS(val, regnum) \
282 (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
284 #define DR7_SET_EXE(val, regnum) \
285 (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
287 #define DR7_SET_WRITE(val, regnum) \
288 (val |= (DR7_BP_WRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
290 #define DR7_SET_ACCESS(val, regnum) \
291 (val |= (DR7_BP_READWRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
293 #define DR7_SET_LENGTH(val, regnum, len) \
294 (val |= (len == 1) ? (DR7_BP_LENGTH_1 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
295 (len == 2) ? (DR7_BP_LENGTH_2 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
296 (DR7_BP_LENGTH_4 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
298 /* public interface */
299 int x86_32_get_gdb_reg_list(struct target
*t
,
300 struct reg
**reg_list
[], int *reg_list_size
,
301 enum target_register_class reg_class
);
302 int x86_32_common_init_arch_info(struct target
*target
,
303 struct x86_32_common
*x86_32
);
304 int x86_32_common_mmu(struct target
*t
, int *enabled
);
305 int x86_32_common_virt2phys(struct target
*t
, uint32_t address
, uint32_t *physical
);
306 int x86_32_common_read_phys_mem(struct target
*t
, uint32_t phys_address
,
307 uint32_t size
, uint32_t count
, uint8_t *buffer
);
308 int x86_32_common_write_phys_mem(struct target
*t
, uint32_t phys_address
,
309 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
310 int x86_32_common_read_memory(struct target
*t
, uint32_t addr
,
311 uint32_t size
, uint32_t count
, uint8_t *buf
);
312 int x86_32_common_write_memory(struct target
*t
, uint32_t addr
,
313 uint32_t size
, uint32_t count
, const uint8_t *buf
);
314 int x86_32_common_read_io(struct target
*t
, uint32_t addr
,
315 uint32_t size
, uint8_t *buf
);
316 int x86_32_common_write_io(struct target
*t
, uint32_t addr
,
317 uint32_t size
, const uint8_t *buf
);
318 int x86_32_common_add_breakpoint(struct target
*t
, struct breakpoint
*bp
);
319 int x86_32_common_remove_breakpoint(struct target
*t
, struct breakpoint
*bp
);
320 int x86_32_common_add_watchpoint(struct target
*t
, struct watchpoint
*wp
);
321 int x86_32_common_remove_watchpoint(struct target
*t
, struct watchpoint
*wp
);
323 #endif /* X86_32_COMMON_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)