Code Review / openocd.git / blob
? search:


77f0f1b8927756906e446f1ad47fb5ff57105ada
[openocd.git] / src / target / xscale.c
1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "breakpoints.h"
31 #include "xscale.h"
32 #include "target_type.h"
33 #include "arm_jtag.h"
34 #include "arm_simulator.h"
35 #include "arm_disassembler.h"
36 #include <helper/time_support.h>
37 #include "register.h"
38 #include "image.h"
39 #include "arm_opcodes.h"
40 #include "armv4_5.h"
41
42
43 /*
44 * Important XScale documents available as of October 2009 include:
45 *
46 * Intel XScale® Core Developer’s Manual, January 2004
47 * Order Number: 273473-002
48 * This has a chapter detailing debug facilities, and punts some
49 * details to chip-specific microarchitecture documents.
50 *
51 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
52 * Document Number: 273539-005
53 * Less detailed than the developer's manual, but summarizes those
54 * missing details (for most XScales) and gives LOTS of notes about
55 * debugger/handler interaction issues. Presents a simpler reset
56 * and load-handler sequence than the arch doc. (Note, OpenOCD
57 * doesn't currently support "Hot-Debug" as defined there.)
58 *
59 * Chip-specific microarchitecture documents may also be useful.
60 */
61
62
63 /* forward declarations */
64 static int xscale_resume(struct target *, int current,
65 uint32_t address, int handle_breakpoints, int debug_execution);
66 static int xscale_debug_entry(struct target *);
67 static int xscale_restore_banked(struct target *);
68 static int xscale_get_reg(struct reg *reg);
69 static int xscale_set_reg(struct reg *reg, uint8_t *buf);
70 static int xscale_set_breakpoint(struct target *, struct breakpoint *);
71 static int xscale_set_watchpoint(struct target *, struct watchpoint *);
72 static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
73 static int xscale_read_trace(struct target *);
74
75
76 /* This XScale "debug handler" is loaded into the processor's
77 * mini-ICache, which is 2K of code writable only via JTAG.
78 *
79 * FIXME the OpenOCD "bin2char" utility currently doesn't handle
80 * binary files cleanly. It's string oriented, and terminates them
81 * with a NUL character. Better would be to generate the constants
82 * and let other code decide names, scoping, and other housekeeping.
83 */
84 static /* unsigned const char xscale_debug_handler[] = ... */
85 #include "xscale_debug.h"
86
87 static char *const xscale_reg_list[] =
88 {
89 "XSCALE_MAINID", /* 0 */
90 "XSCALE_CACHETYPE",
91 "XSCALE_CTRL",
92 "XSCALE_AUXCTRL",
93 "XSCALE_TTB",
94 "XSCALE_DAC",
95 "XSCALE_FSR",
96 "XSCALE_FAR",
97 "XSCALE_PID",
98 "XSCALE_CPACCESS",
99 "XSCALE_IBCR0", /* 10 */
100 "XSCALE_IBCR1",
101 "XSCALE_DBR0",
102 "XSCALE_DBR1",
103 "XSCALE_DBCON",
104 "XSCALE_TBREG",
105 "XSCALE_CHKPT0",
106 "XSCALE_CHKPT1",
107 "XSCALE_DCSR",
108 "XSCALE_TX",
109 "XSCALE_RX", /* 20 */
110 "XSCALE_TXRXCTRL",
111 };
112
113 static const struct xscale_reg xscale_reg_arch_info[] =
114 {
115 {XSCALE_MAINID, NULL},
116 {XSCALE_CACHETYPE, NULL},
117 {XSCALE_CTRL, NULL},
118 {XSCALE_AUXCTRL, NULL},
119 {XSCALE_TTB, NULL},
120 {XSCALE_DAC, NULL},
121 {XSCALE_FSR, NULL},
122 {XSCALE_FAR, NULL},
123 {XSCALE_PID, NULL},
124 {XSCALE_CPACCESS, NULL},
125 {XSCALE_IBCR0, NULL},
126 {XSCALE_IBCR1, NULL},
127 {XSCALE_DBR0, NULL},
128 {XSCALE_DBR1, NULL},
129 {XSCALE_DBCON, NULL},
130 {XSCALE_TBREG, NULL},
131 {XSCALE_CHKPT0, NULL},
132 {XSCALE_CHKPT1, NULL},
133 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
134 {-1, NULL}, /* TX accessed via JTAG */
135 {-1, NULL}, /* RX accessed via JTAG */
136 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
137 };
138
139 /* convenience wrapper to access XScale specific registers */
140 static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
141 {
142 uint8_t buf[4];
143
144 buf_set_u32(buf, 0, 32, value);
145
146 return xscale_set_reg(reg, buf);
147 }
148
149 static const char xscale_not[] = "target is not an XScale";
150
151 static int xscale_verify_pointer(struct command_context *cmd_ctx,
152 struct xscale_common *xscale)
153 {
154 if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
155 command_print(cmd_ctx, xscale_not);
156 return ERROR_TARGET_INVALID;
157 }
158 return ERROR_OK;
159 }
160
161 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
162 {
163 assert (tap != NULL);
164
165 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
166 {
167 struct scan_field field;
168 uint8_t scratch[4];
169
170 memset(&field, 0, sizeof field);
171 field.num_bits = tap->ir_length;
172 field.out_value = scratch;
173 buf_set_u32(scratch, 0, field.num_bits, new_instr);
174
175 jtag_add_ir_scan(tap, &field, end_state);
176 }
177
178 return ERROR_OK;
179 }
180
181 static int xscale_read_dcsr(struct target *target)
182 {
183 struct xscale_common *xscale = target_to_xscale(target);
184 int retval;
185 struct scan_field fields[3];
186 uint8_t field0 = 0x0;
187 uint8_t field0_check_value = 0x2;
188 uint8_t field0_check_mask = 0x7;
189 uint8_t field2 = 0x0;
190 uint8_t field2_check_value = 0x0;
191 uint8_t field2_check_mask = 0x1;
192
193 xscale_jtag_set_instr(target->tap,
194 XSCALE_SELDCSR << xscale->xscale_variant,
195 TAP_DRPAUSE);
196
197 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
198 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
199
200 memset(&fields, 0, sizeof fields);
201
202 fields[0].num_bits = 3;
203 fields[0].out_value = &field0;
204 uint8_t tmp;
205 fields[0].in_value = &tmp;
206
207 fields[1].num_bits = 32;
208 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
209
210 fields[2].num_bits = 1;
211 fields[2].out_value = &field2;
212 uint8_t tmp2;
213 fields[2].in_value = &tmp2;
214
215 jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
216
217 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
218 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
219
220 if ((retval = jtag_execute_queue()) != ERROR_OK)
221 {
222 LOG_ERROR("JTAG error while reading DCSR");
223 return retval;
224 }
225
226 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
227 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
228
229 /* write the register with the value we just read
230 * on this second pass, only the first bit of field0 is guaranteed to be 0)
231 */
232 field0_check_mask = 0x1;
233 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
234 fields[1].in_value = NULL;
235
236 jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
237
238 /* DANGER!!! this must be here. It will make sure that the arguments
239 * to jtag_set_check_value() does not go out of scope! */
240 return jtag_execute_queue();
241 }
242
243
244 static void xscale_getbuf(jtag_callback_data_t arg)
245 {
246 uint8_t *in = (uint8_t *)arg;
247 *((uint32_t *)in) = buf_get_u32(in, 0, 32);
248 }
249
250 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
251 {
252 if (num_words == 0)
253 return ERROR_INVALID_ARGUMENTS;
254
255 struct xscale_common *xscale = target_to_xscale(target);
256 int retval = ERROR_OK;
257 tap_state_t path[3];
258 struct scan_field fields[3];
259 uint8_t *field0 = malloc(num_words * 1);
260 uint8_t field0_check_value = 0x2;
261 uint8_t field0_check_mask = 0x6;
262 uint32_t *field1 = malloc(num_words * 4);
263 uint8_t field2_check_value = 0x0;
264 uint8_t field2_check_mask = 0x1;
265 int words_done = 0;
266 int words_scheduled = 0;
267 int i;
268
269 path[0] = TAP_DRSELECT;
270 path[1] = TAP_DRCAPTURE;
271 path[2] = TAP_DRSHIFT;
272
273 memset(&fields, 0, sizeof fields);
274
275 fields[0].num_bits = 3;
276 fields[0].check_value = &field0_check_value;
277 fields[0].check_mask = &field0_check_mask;
278
279 fields[1].num_bits = 32;
280
281 fields[2].num_bits = 1;
282 fields[2].check_value = &field2_check_value;
283 fields[2].check_mask = &field2_check_mask;
284
285 xscale_jtag_set_instr(target->tap,
286 XSCALE_DBGTX << xscale->xscale_variant,
287 TAP_IDLE);
288 jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
289
290 /* repeat until all words have been collected */
291 int attempts = 0;
292 while (words_done < num_words)
293 {
294 /* schedule reads */
295 words_scheduled = 0;
296 for (i = words_done; i < num_words; i++)
297 {
298 fields[0].in_value = &field0[i];
299
300 jtag_add_pathmove(3, path);
301
302 fields[1].in_value = (uint8_t *)(field1 + i);
303
304 jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
305
306 jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
307
308 words_scheduled++;
309 }
310
311 if ((retval = jtag_execute_queue()) != ERROR_OK)
312 {
313 LOG_ERROR("JTAG error while receiving data from debug handler");
314 break;
315 }
316
317 /* examine results */
318 for (i = words_done; i < num_words; i++)
319 {
320 if (!(field0[0] & 1))
321 {
322 /* move backwards if necessary */
323 int j;
324 for (j = i; j < num_words - 1; j++)
325 {
326 field0[j] = field0[j + 1];
327 field1[j] = field1[j + 1];
328 }
329 words_scheduled--;
330 }
331 }
332 if (words_scheduled == 0)
333 {
334 if (attempts++==1000)
335 {
336 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
337 retval = ERROR_TARGET_TIMEOUT;
338 break;
339 }
340 }
341
342 words_done += words_scheduled;
343 }
344
345 for (i = 0; i < num_words; i++)
346 *(buffer++) = buf_get_u32((uint8_t*)&field1[i], 0, 32);
347
348 free(field1);
349
350 return retval;
351 }
352
353 static int xscale_read_tx(struct target *target, int consume)
354 {
355 struct xscale_common *xscale = target_to_xscale(target);
356 tap_state_t path[3];
357 tap_state_t noconsume_path[6];
358 int retval;
359 struct timeval timeout, now;
360 struct scan_field fields[3];
361 uint8_t field0_in = 0x0;
362 uint8_t field0_check_value = 0x2;
363 uint8_t field0_check_mask = 0x6;
364 uint8_t field2_check_value = 0x0;
365 uint8_t field2_check_mask = 0x1;
366
367 xscale_jtag_set_instr(target->tap,
368 XSCALE_DBGTX << xscale->xscale_variant,
369 TAP_IDLE);
370
371 path[0] = TAP_DRSELECT;
372 path[1] = TAP_DRCAPTURE;
373 path[2] = TAP_DRSHIFT;
374
375 noconsume_path[0] = TAP_DRSELECT;
376 noconsume_path[1] = TAP_DRCAPTURE;
377 noconsume_path[2] = TAP_DREXIT1;
378 noconsume_path[3] = TAP_DRPAUSE;
379 noconsume_path[4] = TAP_DREXIT2;
380 noconsume_path[5] = TAP_DRSHIFT;
381
382 memset(&fields, 0, sizeof fields);
383
384 fields[0].num_bits = 3;
385 fields[0].in_value = &field0_in;
386
387 fields[1].num_bits = 32;
388 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
389
390 fields[2].num_bits = 1;
391 uint8_t tmp;
392 fields[2].in_value = &tmp;
393
394 gettimeofday(&timeout, NULL);
395 timeval_add_time(&timeout, 1, 0);
396
397 for (;;)
398 {
399 /* if we want to consume the register content (i.e. clear TX_READY),
400 * we have to go straight from Capture-DR to Shift-DR
401 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
402 */
403 if (consume)
404 jtag_add_pathmove(3, path);
405 else
406 {
407 jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
408 }
409
410 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
411
412 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
413 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
414
415 if ((retval = jtag_execute_queue()) != ERROR_OK)
416 {
417 LOG_ERROR("JTAG error while reading TX");
418 return ERROR_TARGET_TIMEOUT;
419 }
420
421 gettimeofday(&now, NULL);
422 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
423 {
424 LOG_ERROR("time out reading TX register");
425 return ERROR_TARGET_TIMEOUT;
426 }
427 if (!((!(field0_in & 1)) && consume))
428 {
429 goto done;
430 }
431 if (debug_level >= 3)
432 {
433 LOG_DEBUG("waiting 100ms");
434 alive_sleep(100); /* avoid flooding the logs */
435 } else
436 {
437 keep_alive();
438 }
439 }
440 done:
441
442 if (!(field0_in & 1))
443 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
444
445 return ERROR_OK;
446 }
447
448 static int xscale_write_rx(struct target *target)
449 {
450 struct xscale_common *xscale = target_to_xscale(target);
451 int retval;
452 struct timeval timeout, now;
453 struct scan_field fields[3];
454 uint8_t field0_out = 0x0;
455 uint8_t field0_in = 0x0;
456 uint8_t field0_check_value = 0x2;
457 uint8_t field0_check_mask = 0x6;
458 uint8_t field2 = 0x0;
459 uint8_t field2_check_value = 0x0;
460 uint8_t field2_check_mask = 0x1;
461
462 xscale_jtag_set_instr(target->tap,
463 XSCALE_DBGRX << xscale->xscale_variant,
464 TAP_IDLE);
465
466 memset(&fields, 0, sizeof fields);
467
468 fields[0].num_bits = 3;
469 fields[0].out_value = &field0_out;
470 fields[0].in_value = &field0_in;
471
472 fields[1].num_bits = 32;
473 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
474
475 fields[2].num_bits = 1;
476 fields[2].out_value = &field2;
477 uint8_t tmp;
478 fields[2].in_value = &tmp;
479
480 gettimeofday(&timeout, NULL);
481 timeval_add_time(&timeout, 1, 0);
482
483 /* poll until rx_read is low */
484 LOG_DEBUG("polling RX");
485 for (;;)
486 {
487 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
488
489 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
490 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
491
492 if ((retval = jtag_execute_queue()) != ERROR_OK)
493 {
494 LOG_ERROR("JTAG error while writing RX");
495 return retval;
496 }
497
498 gettimeofday(&now, NULL);
499 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
500 {
501 LOG_ERROR("time out writing RX register");
502 return ERROR_TARGET_TIMEOUT;
503 }
504 if (!(field0_in & 1))
505 goto done;
506 if (debug_level >= 3)
507 {
508 LOG_DEBUG("waiting 100ms");
509 alive_sleep(100); /* avoid flooding the logs */
510 } else
511 {
512 keep_alive();
513 }
514 }
515 done:
516
517 /* set rx_valid */
518 field2 = 0x1;
519 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
520
521 if ((retval = jtag_execute_queue()) != ERROR_OK)
522 {
523 LOG_ERROR("JTAG error while writing RX");
524 return retval;
525 }
526
527 return ERROR_OK;
528 }
529
530 /* send count elements of size byte to the debug handler */
531 static int xscale_send(struct target *target, uint8_t *buffer, int count, int size)
532 {
533 struct xscale_common *xscale = target_to_xscale(target);
534 uint32_t t[3];
535 int bits[3];
536 int retval;
537 int done_count = 0;
538
539 xscale_jtag_set_instr(target->tap,
540 XSCALE_DBGRX << xscale->xscale_variant,
541 TAP_IDLE);
542
543 bits[0]=3;
544 t[0]=0;
545 bits[1]=32;
546 t[2]=1;
547 bits[2]=1;
548 int endianness = target->endianness;
549 while (done_count++ < count)
550 {
551 switch (size)
552 {
553 case 4:
554 if (endianness == TARGET_LITTLE_ENDIAN)
555 {
556 t[1]=le_to_h_u32(buffer);
557 } else
558 {
559 t[1]=be_to_h_u32(buffer);
560 }
561 break;
562 case 2:
563 if (endianness == TARGET_LITTLE_ENDIAN)
564 {
565 t[1]=le_to_h_u16(buffer);
566 } else
567 {
568 t[1]=be_to_h_u16(buffer);
569 }
570 break;
571 case 1:
572 t[1]=buffer[0];
573 break;
574 default:
575 LOG_ERROR("BUG: size neither 4, 2 nor 1");
576 return ERROR_INVALID_ARGUMENTS;
577 }
578 jtag_add_dr_out(target->tap,
579 3,
580 bits,
581 t,
582 TAP_IDLE);
583 buffer += size;
584 }
585
586 if ((retval = jtag_execute_queue()) != ERROR_OK)
587 {
588 LOG_ERROR("JTAG error while sending data to debug handler");
589 return retval;
590 }
591
592 return ERROR_OK;
593 }
594
595 static int xscale_send_u32(struct target *target, uint32_t value)
596 {
597 struct xscale_common *xscale = target_to_xscale(target);
598
599 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
600 return xscale_write_rx(target);
601 }
602
603 static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
604 {
605 struct xscale_common *xscale = target_to_xscale(target);
606 int retval;
607 struct scan_field fields[3];
608 uint8_t field0 = 0x0;
609 uint8_t field0_check_value = 0x2;
610 uint8_t field0_check_mask = 0x7;
611 uint8_t field2 = 0x0;
612 uint8_t field2_check_value = 0x0;
613 uint8_t field2_check_mask = 0x1;
614
615 if (hold_rst != -1)
616 xscale->hold_rst = hold_rst;
617
618 if (ext_dbg_brk != -1)
619 xscale->external_debug_break = ext_dbg_brk;
620
621 xscale_jtag_set_instr(target->tap,
622 XSCALE_SELDCSR << xscale->xscale_variant,
623 TAP_IDLE);
624
625 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
626 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
627
628 memset(&fields, 0, sizeof fields);
629
630 fields[0].num_bits = 3;
631 fields[0].out_value = &field0;
632 uint8_t tmp;
633 fields[0].in_value = &tmp;
634
635 fields[1].num_bits = 32;
636 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
637
638 fields[2].num_bits = 1;
639 fields[2].out_value = &field2;
640 uint8_t tmp2;
641 fields[2].in_value = &tmp2;
642
643 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
644
645 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
646 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
647
648 if ((retval = jtag_execute_queue()) != ERROR_OK)
649 {
650 LOG_ERROR("JTAG error while writing DCSR");
651 return retval;
652 }
653
654 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
655 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
656
657 return ERROR_OK;
658 }
659
660 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
661 static unsigned int parity (unsigned int v)
662 {
663 // unsigned int ov = v;
664 v ^= v >> 16;
665 v ^= v >> 8;
666 v ^= v >> 4;
667 v &= 0xf;
668 // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
669 return (0x6996 >> v) & 1;
670 }
671
672 static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
673 {
674 struct xscale_common *xscale = target_to_xscale(target);
675 uint8_t packet[4];
676 uint8_t cmd;
677 int word;
678 struct scan_field fields[2];
679
680 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
681
682 /* LDIC into IR */
683 xscale_jtag_set_instr(target->tap,
684 XSCALE_LDIC << xscale->xscale_variant,
685 TAP_IDLE);
686
687 /* CMD is b011 to load a cacheline into the Mini ICache.
688 * Loading into the main ICache is deprecated, and unused.
689 * It's followed by three zero bits, and 27 address bits.
690 */
691 buf_set_u32(&cmd, 0, 6, 0x3);
692
693 /* virtual address of desired cache line */
694 buf_set_u32(packet, 0, 27, va >> 5);
695
696 memset(&fields, 0, sizeof fields);
697
698 fields[0].num_bits = 6;
699 fields[0].out_value = &cmd;
700
701 fields[1].num_bits = 27;
702 fields[1].out_value = packet;
703
704 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
705
706 /* rest of packet is a cacheline: 8 instructions, with parity */
707 fields[0].num_bits = 32;
708 fields[0].out_value = packet;
709
710 fields[1].num_bits = 1;
711 fields[1].out_value = &cmd;
712
713 for (word = 0; word < 8; word++)
714 {
715 buf_set_u32(packet, 0, 32, buffer[word]);
716
717 uint32_t value;
718 memcpy(&value, packet, sizeof(uint32_t));
719 cmd = parity(value);
720
721 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
722 }
723
724 return jtag_execute_queue();
725 }
726
727 static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
728 {
729 struct xscale_common *xscale = target_to_xscale(target);
730 uint8_t packet[4];
731 uint8_t cmd;
732 struct scan_field fields[2];
733
734 xscale_jtag_set_instr(target->tap,
735 XSCALE_LDIC << xscale->xscale_variant,
736 TAP_IDLE);
737
738 /* CMD for invalidate IC line b000, bits [6:4] b000 */
739 buf_set_u32(&cmd, 0, 6, 0x0);
740
741 /* virtual address of desired cache line */
742 buf_set_u32(packet, 0, 27, va >> 5);
743
744 memset(&fields, 0, sizeof fields);
745
746 fields[0].num_bits = 6;
747 fields[0].out_value = &cmd;
748
749 fields[1].num_bits = 27;
750 fields[1].out_value = packet;
751
752 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
753
754 return ERROR_OK;
755 }
756
757 static int xscale_update_vectors(struct target *target)
758 {
759 struct xscale_common *xscale = target_to_xscale(target);
760 int i;
761 int retval;
762
763 uint32_t low_reset_branch, high_reset_branch;
764
765 for (i = 1; i < 8; i++)
766 {
767 /* if there's a static vector specified for this exception, override */
768 if (xscale->static_high_vectors_set & (1 << i))
769 {
770 xscale->high_vectors[i] = xscale->static_high_vectors[i];
771 }
772 else
773 {
774 retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
775 if (retval == ERROR_TARGET_TIMEOUT)
776 return retval;
777 if (retval != ERROR_OK)
778 {
779 /* Some of these reads will fail as part of normal execution */
780 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
781 }
782 }
783 }
784
785 for (i = 1; i < 8; i++)
786 {
787 if (xscale->static_low_vectors_set & (1 << i))
788 {
789 xscale->low_vectors[i] = xscale->static_low_vectors[i];
790 }
791 else
792 {
793 retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
794 if (retval == ERROR_TARGET_TIMEOUT)
795 return retval;
796 if (retval != ERROR_OK)
797 {
798 /* Some of these reads will fail as part of normal execution */
799 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
800 }
801 }
802 }
803
804 /* calculate branches to debug handler */
805 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
806 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
807
808 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
809 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
810
811 /* invalidate and load exception vectors in mini i-cache */
812 xscale_invalidate_ic_line(target, 0x0);
813 xscale_invalidate_ic_line(target, 0xffff0000);
814
815 xscale_load_ic(target, 0x0, xscale->low_vectors);
816 xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
817
818 return ERROR_OK;
819 }
820
821 static int xscale_arch_state(struct target *target)
822 {
823 struct xscale_common *xscale = target_to_xscale(target);
824 struct arm *armv4_5 = &xscale->armv4_5_common;
825
826 static const char *state[] =
827 {
828 "disabled", "enabled"
829 };
830
831 static const char *arch_dbg_reason[] =
832 {
833 "", "\n(processor reset)", "\n(trace buffer full)"
834 };
835
836 if (armv4_5->common_magic != ARM_COMMON_MAGIC)
837 {
838 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
839 return ERROR_INVALID_ARGUMENTS;
840 }
841
842 arm_arch_state(target);
843 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
844 state[xscale->armv4_5_mmu.mmu_enabled],
845 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
846 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
847 arch_dbg_reason[xscale->arch_debug_reason]);
848
849 return ERROR_OK;
850 }
851
852 static int xscale_poll(struct target *target)
853 {
854 int retval = ERROR_OK;
855
856 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
857 {
858 enum target_state previous_state = target->state;
859 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
860 {
861
862 /* there's data to read from the tx register, we entered debug state */
863 target->state = TARGET_HALTED;
864
865 /* process debug entry, fetching current mode regs */
866 retval = xscale_debug_entry(target);
867 }
868 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
869 {
870 LOG_USER("error while polling TX register, reset CPU");
871 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
872 target->state = TARGET_HALTED;
873 }
874
875 /* debug_entry could have overwritten target state (i.e. immediate resume)
876 * don't signal event handlers in that case
877 */
878 if (target->state != TARGET_HALTED)
879 return ERROR_OK;
880
881 /* if target was running, signal that we halted
882 * otherwise we reentered from debug execution */
883 if (previous_state == TARGET_RUNNING)
884 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
885 else
886 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
887 }
888
889 return retval;
890 }
891
892 static int xscale_debug_entry(struct target *target)
893 {
894 struct xscale_common *xscale = target_to_xscale(target);
895 struct arm *armv4_5 = &xscale->armv4_5_common;
896 uint32_t pc;
897 uint32_t buffer[10];
898 unsigned i;
899 int retval;
900 uint32_t moe;
901
902 /* clear external dbg break (will be written on next DCSR read) */
903 xscale->external_debug_break = 0;
904 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
905 return retval;
906
907 /* get r0, pc, r1 to r7 and cpsr */
908 if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK)
909 return retval;
910
911 /* move r0 from buffer to register cache */
912 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
913 armv4_5->core_cache->reg_list[0].dirty = 1;
914 armv4_5->core_cache->reg_list[0].valid = 1;
915 LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
916
917 /* move pc from buffer to register cache */
918 buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]);
919 armv4_5->pc->dirty = 1;
920 armv4_5->pc->valid = 1;
921 LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
922
923 /* move data from buffer to register cache */
924 for (i = 1; i <= 7; i++)
925 {
926 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
927 armv4_5->core_cache->reg_list[i].dirty = 1;
928 armv4_5->core_cache->reg_list[i].valid = 1;
929 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
930 }
931
932 arm_set_cpsr(armv4_5, buffer[9]);
933 LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
934
935 if (!is_arm_mode(armv4_5->core_mode))
936 {
937 target->state = TARGET_UNKNOWN;
938 LOG_ERROR("cpsr contains invalid mode value - communication failure");
939 return ERROR_TARGET_FAILURE;
940 }
941 LOG_DEBUG("target entered debug state in %s mode",
942 arm_mode_name(armv4_5->core_mode));
943
944 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
945 if (armv4_5->spsr) {
946 xscale_receive(target, buffer, 8);
947 buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]);
948 armv4_5->spsr->dirty = false;
949 armv4_5->spsr->valid = true;
950 }
951 else
952 {
953 /* r8 to r14, but no spsr */
954 xscale_receive(target, buffer, 7);
955 }
956
957 /* move data from buffer to right banked register in cache */
958 for (i = 8; i <= 14; i++)
959 {
960 struct reg *r = arm_reg_current(armv4_5, i);
961
962 buf_set_u32(r->value, 0, 32, buffer[i - 8]);
963 r->dirty = false;
964 r->valid = true;
965 }
966
967 /* mark xscale regs invalid to ensure they are retrieved from the
968 * debug handler if requested */
969 for (i = 0; i < xscale->reg_cache->num_regs; i++)
970 xscale->reg_cache->reg_list[i].valid = 0;
971
972 /* examine debug reason */
973 xscale_read_dcsr(target);
974 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
975
976 /* stored PC (for calculating fixup) */
977 pc = buf_get_u32(armv4_5->pc->value, 0, 32);
978
979 switch (moe)
980 {
981 case 0x0: /* Processor reset */
982 target->debug_reason = DBG_REASON_DBGRQ;
983 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
984 pc -= 4;
985 break;
986 case 0x1: /* Instruction breakpoint hit */
987 target->debug_reason = DBG_REASON_BREAKPOINT;
988 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
989 pc -= 4;
990 break;
991 case 0x2: /* Data breakpoint hit */
992 target->debug_reason = DBG_REASON_WATCHPOINT;
993 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
994 pc -= 4;
995 break;
996 case 0x3: /* BKPT instruction executed */
997 target->debug_reason = DBG_REASON_BREAKPOINT;
998 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
999 pc -= 4;
1000 break;
1001 case 0x4: /* Ext. debug event */
1002 target->debug_reason = DBG_REASON_DBGRQ;
1003 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1004 pc -= 4;
1005 break;
1006 case 0x5: /* Vector trap occured */
1007 target->debug_reason = DBG_REASON_BREAKPOINT;
1008 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1009 pc -= 4;
1010 break;
1011 case 0x6: /* Trace buffer full break */
1012 target->debug_reason = DBG_REASON_DBGRQ;
1013 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1014 pc -= 4;
1015 break;
1016 case 0x7: /* Reserved (may flag Hot-Debug support) */
1017 default:
1018 LOG_ERROR("Method of Entry is 'Reserved'");
1019 exit(-1);
1020 break;
1021 }
1022
1023 /* apply PC fixup */
1024 buf_set_u32(armv4_5->pc->value, 0, 32, pc);
1025
1026 /* on the first debug entry, identify cache type */
1027 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1028 {
1029 uint32_t cache_type_reg;
1030
1031 /* read cp15 cache type register */
1032 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1033 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1034
1035 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1036 }
1037
1038 /* examine MMU and Cache settings */
1039 /* read cp15 control register */
1040 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1041 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1042 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1043 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1044 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1045
1046 /* tracing enabled, read collected trace data */
1047 if (xscale->trace.buffer_enabled)
1048 {
1049 xscale_read_trace(target);
1050 xscale->trace.buffer_fill--;
1051
1052 /* resume if we're still collecting trace data */
1053 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1054 && (xscale->trace.buffer_fill > 0))
1055 {
1056 xscale_resume(target, 1, 0x0, 1, 0);
1057 }
1058 else
1059 {
1060 xscale->trace.buffer_enabled = 0;
1061 }
1062 }
1063
1064 return ERROR_OK;
1065 }
1066
1067 static int xscale_halt(struct target *target)
1068 {
1069 struct xscale_common *xscale = target_to_xscale(target);
1070
1071 LOG_DEBUG("target->state: %s",
1072 target_state_name(target));
1073
1074 if (target->state == TARGET_HALTED)
1075 {
1076 LOG_DEBUG("target was already halted");
1077 return ERROR_OK;
1078 }
1079 else if (target->state == TARGET_UNKNOWN)
1080 {
1081 /* this must not happen for a xscale target */
1082 LOG_ERROR("target was in unknown state when halt was requested");
1083 return ERROR_TARGET_INVALID;
1084 }
1085 else if (target->state == TARGET_RESET)
1086 {
1087 LOG_DEBUG("target->state == TARGET_RESET");
1088 }
1089 else
1090 {
1091 /* assert external dbg break */
1092 xscale->external_debug_break = 1;
1093 xscale_read_dcsr(target);
1094
1095 target->debug_reason = DBG_REASON_DBGRQ;
1096 }
1097
1098 return ERROR_OK;
1099 }
1100
1101 static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
1102 {
1103 struct xscale_common *xscale = target_to_xscale(target);
1104 struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1105 int retval;
1106
1107 if (xscale->ibcr0_used)
1108 {
1109 struct breakpoint *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1110
1111 if (ibcr0_bp)
1112 {
1113 xscale_unset_breakpoint(target, ibcr0_bp);
1114 }
1115 else
1116 {
1117 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1118 exit(-1);
1119 }
1120 }
1121
1122 if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
1123 return retval;
1124
1125 return ERROR_OK;
1126 }
1127
1128 static int xscale_disable_single_step(struct target *target)
1129 {
1130 struct xscale_common *xscale = target_to_xscale(target);
1131 struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1132 int retval;
1133
1134 if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
1135 return retval;
1136
1137 return ERROR_OK;
1138 }
1139
1140 static void xscale_enable_watchpoints(struct target *target)
1141 {
1142 struct watchpoint *watchpoint = target->watchpoints;
1143
1144 while (watchpoint)
1145 {
1146 if (watchpoint->set == 0)
1147 xscale_set_watchpoint(target, watchpoint);
1148 watchpoint = watchpoint->next;
1149 }
1150 }
1151
1152 static void xscale_enable_breakpoints(struct target *target)
1153 {
1154 struct breakpoint *breakpoint = target->breakpoints;
1155
1156 /* set any pending breakpoints */
1157 while (breakpoint)
1158 {
1159 if (breakpoint->set == 0)
1160 xscale_set_breakpoint(target, breakpoint);
1161 breakpoint = breakpoint->next;
1162 }
1163 }
1164
1165 static int xscale_resume(struct target *target, int current,
1166 uint32_t address, int handle_breakpoints, int debug_execution)
1167 {
1168 struct xscale_common *xscale = target_to_xscale(target);
1169 struct arm *armv4_5 = &xscale->armv4_5_common;
1170 struct breakpoint *breakpoint = target->breakpoints;
1171 uint32_t current_pc;
1172 int retval;
1173 int i;
1174
1175 LOG_DEBUG("-");
1176
1177 if (target->state != TARGET_HALTED)
1178 {
1179 LOG_WARNING("target not halted");
1180 return ERROR_TARGET_NOT_HALTED;
1181 }
1182
1183 if (!debug_execution)
1184 {
1185 target_free_all_working_areas(target);
1186 }
1187
1188 /* update vector tables */
1189 if ((retval = xscale_update_vectors(target)) != ERROR_OK)
1190 return retval;
1191
1192 /* current = 1: continue on current pc, otherwise continue at <address> */
1193 if (!current)
1194 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1195
1196 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1197
1198 /* if we're at the reset vector, we have to simulate the branch */
1199 if (current_pc == 0x0)
1200 {
1201 arm_simulate_step(target, NULL);
1202 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1203 }
1204
1205 /* the front-end may request us not to handle breakpoints */
1206 if (handle_breakpoints)
1207 {
1208 breakpoint = breakpoint_find(target,
1209 buf_get_u32(armv4_5->pc->value, 0, 32));
1210 if (breakpoint != NULL)
1211 {
1212 uint32_t next_pc;
1213 int saved_trace_buffer_enabled;
1214
1215 /* there's a breakpoint at the current PC, we have to step over it */
1216 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1217 xscale_unset_breakpoint(target, breakpoint);
1218
1219 /* calculate PC of next instruction */
1220 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1221 {
1222 uint32_t current_opcode;
1223 target_read_u32(target, current_pc, &current_opcode);
1224 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1225 }
1226
1227 LOG_DEBUG("enable single-step");
1228 xscale_enable_single_step(target, next_pc);
1229
1230 /* restore banked registers */
1231 retval = xscale_restore_banked(target);
1232
1233 /* send resume request */
1234 xscale_send_u32(target, 0x30);
1235
1236 /* send CPSR */
1237 xscale_send_u32(target,
1238 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1239 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1240 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1241
1242 for (i = 7; i >= 0; i--)
1243 {
1244 /* send register */
1245 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1246 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1247 }
1248
1249 /* send PC */
1250 xscale_send_u32(target,
1251 buf_get_u32(armv4_5->pc->value, 0, 32));
1252 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1253 buf_get_u32(armv4_5->pc->value, 0, 32));
1254
1255 /* disable trace data collection in xscale_debug_entry() */
1256 saved_trace_buffer_enabled = xscale->trace.buffer_enabled;
1257 xscale->trace.buffer_enabled = 0;
1258
1259 /* wait for and process debug entry */
1260 xscale_debug_entry(target);
1261
1262 /* re-enable trace buffer, if enabled previously */
1263 xscale->trace.buffer_enabled = saved_trace_buffer_enabled;
1264
1265 LOG_DEBUG("disable single-step");
1266 xscale_disable_single_step(target);
1267
1268 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1269 xscale_set_breakpoint(target, breakpoint);
1270 }
1271 }
1272
1273 /* enable any pending breakpoints and watchpoints */
1274 xscale_enable_breakpoints(target);
1275 xscale_enable_watchpoints(target);
1276
1277 /* restore banked registers */
1278 retval = xscale_restore_banked(target);
1279
1280 /* send resume request (command 0x30 or 0x31)
1281 * clean the trace buffer if it is to be enabled (0x62) */
1282 if (xscale->trace.buffer_enabled)
1283 {
1284 xscale_send_u32(target, 0x62);
1285 xscale_send_u32(target, 0x31);
1286 }
1287 else
1288 xscale_send_u32(target, 0x30);
1289
1290 /* send CPSR */
1291 xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
1292 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1293 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1294
1295 for (i = 7; i >= 0; i--)
1296 {
1297 /* send register */
1298 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1299 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1300 }
1301
1302 /* send PC */
1303 xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32));
1304 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1305 buf_get_u32(armv4_5->pc->value, 0, 32));
1306
1307 target->debug_reason = DBG_REASON_NOTHALTED;
1308
1309 if (!debug_execution)
1310 {
1311 /* registers are now invalid */
1312 register_cache_invalidate(armv4_5->core_cache);
1313 target->state = TARGET_RUNNING;
1314 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1315 }
1316 else
1317 {
1318 target->state = TARGET_DEBUG_RUNNING;
1319 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1320 }
1321
1322 LOG_DEBUG("target resumed");
1323
1324 return ERROR_OK;
1325 }
1326
1327 static int xscale_step_inner(struct target *target, int current,
1328 uint32_t address, int handle_breakpoints)
1329 {
1330 struct xscale_common *xscale = target_to_xscale(target);
1331 struct arm *armv4_5 = &xscale->armv4_5_common;
1332 uint32_t next_pc;
1333 int retval;
1334 int i;
1335
1336 target->debug_reason = DBG_REASON_SINGLESTEP;
1337
1338 /* calculate PC of next instruction */
1339 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1340 {
1341 uint32_t current_opcode, current_pc;
1342 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1343
1344 target_read_u32(target, current_pc, &current_opcode);
1345 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1346 return retval;
1347 }
1348
1349 LOG_DEBUG("enable single-step");
1350 if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK)
1351 return retval;
1352
1353 /* restore banked registers */
1354 if ((retval = xscale_restore_banked(target)) != ERROR_OK)
1355 return retval;
1356
1357 /* send resume request (command 0x30 or 0x31)
1358 * clean the trace buffer if it is to be enabled (0x62) */
1359 if (xscale->trace.buffer_enabled)
1360 {
1361 if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK)
1362 return retval;
1363 if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK)
1364 return retval;
1365 }
1366 else
1367 if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK)
1368 return retval;
1369
1370 /* send CPSR */
1371 retval = xscale_send_u32(target,
1372 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1373 if (retval != ERROR_OK)
1374 return retval;
1375 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1376 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1377
1378 for (i = 7; i >= 0; i--)
1379 {
1380 /* send register */
1381 if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
1382 return retval;
1383 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1384 }
1385
1386 /* send PC */
1387 retval = xscale_send_u32(target,
1388 buf_get_u32(armv4_5->pc->value, 0, 32));
1389 if (retval != ERROR_OK)
1390 return retval;
1391 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1392 buf_get_u32(armv4_5->pc->value, 0, 32));
1393
1394 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1395
1396 /* registers are now invalid */
1397 register_cache_invalidate(armv4_5->core_cache);
1398
1399 /* wait for and process debug entry */
1400 if ((retval = xscale_debug_entry(target)) != ERROR_OK)
1401 return retval;
1402
1403 LOG_DEBUG("disable single-step");
1404 if ((retval = xscale_disable_single_step(target)) != ERROR_OK)
1405 return retval;
1406
1407 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1408
1409 return ERROR_OK;
1410 }
1411
1412 static int xscale_step(struct target *target, int current,
1413 uint32_t address, int handle_breakpoints)
1414 {
1415 struct arm *armv4_5 = target_to_arm(target);
1416 struct breakpoint *breakpoint = NULL;
1417
1418 uint32_t current_pc;
1419 int retval;
1420
1421 if (target->state != TARGET_HALTED)
1422 {
1423 LOG_WARNING("target not halted");
1424 return ERROR_TARGET_NOT_HALTED;
1425 }
1426
1427 /* current = 1: continue on current pc, otherwise continue at <address> */
1428 if (!current)
1429 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1430
1431 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1432
1433 /* if we're at the reset vector, we have to simulate the step */
1434 if (current_pc == 0x0)
1435 {
1436 if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
1437 return retval;
1438 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1439
1440 target->debug_reason = DBG_REASON_SINGLESTEP;
1441 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1442
1443 return ERROR_OK;
1444 }
1445
1446 /* the front-end may request us not to handle breakpoints */
1447 if (handle_breakpoints)
1448 breakpoint = breakpoint_find(target,
1449 buf_get_u32(armv4_5->pc->value, 0, 32));
1450 if (breakpoint != NULL) {
1451 retval = xscale_unset_breakpoint(target, breakpoint);
1452 if (retval != ERROR_OK)
1453 return retval;
1454 }
1455
1456 retval = xscale_step_inner(target, current, address, handle_breakpoints);
1457
1458 if (breakpoint)
1459 {
1460 xscale_set_breakpoint(target, breakpoint);
1461 }
1462
1463 LOG_DEBUG("target stepped");
1464
1465 return ERROR_OK;
1466
1467 }
1468
1469 static int xscale_assert_reset(struct target *target)
1470 {
1471 struct xscale_common *xscale = target_to_xscale(target);
1472
1473 LOG_DEBUG("target->state: %s",
1474 target_state_name(target));
1475
1476 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1477 * end up in T-L-R, which would reset JTAG
1478 */
1479 xscale_jtag_set_instr(target->tap,
1480 XSCALE_SELDCSR << xscale->xscale_variant,
1481 TAP_IDLE);
1482
1483 /* set Hold reset, Halt mode and Trap Reset */
1484 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1485 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1486 xscale_write_dcsr(target, 1, 0);
1487
1488 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1489 xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
1490 jtag_execute_queue();
1491
1492 /* assert reset */
1493 jtag_add_reset(0, 1);
1494
1495 /* sleep 1ms, to be sure we fulfill any requirements */
1496 jtag_add_sleep(1000);
1497 jtag_execute_queue();
1498
1499 target->state = TARGET_RESET;
1500
1501 if (target->reset_halt)
1502 {
1503 int retval;
1504 if ((retval = target_halt(target)) != ERROR_OK)
1505 return retval;
1506 }
1507
1508 return ERROR_OK;
1509 }
1510
1511 static int xscale_deassert_reset(struct target *target)
1512 {
1513 struct xscale_common *xscale = target_to_xscale(target);
1514 struct breakpoint *breakpoint = target->breakpoints;
1515
1516 LOG_DEBUG("-");
1517
1518 xscale->ibcr_available = 2;
1519 xscale->ibcr0_used = 0;
1520 xscale->ibcr1_used = 0;
1521
1522 xscale->dbr_available = 2;
1523 xscale->dbr0_used = 0;
1524 xscale->dbr1_used = 0;
1525
1526 /* mark all hardware breakpoints as unset */
1527 while (breakpoint)
1528 {
1529 if (breakpoint->type == BKPT_HARD)
1530 {
1531 breakpoint->set = 0;
1532 }
1533 breakpoint = breakpoint->next;
1534 }
1535
1536 register_cache_invalidate(xscale->armv4_5_common.core_cache);
1537
1538 /* FIXME mark hardware watchpoints got unset too. Also,
1539 * at least some of the XScale registers are invalid...
1540 */
1541
1542 /*
1543 * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
1544 * contents got invalidated. Safer to force that, so writing new
1545 * contents can't ever fail..
1546 */
1547 {
1548 uint32_t address;
1549 unsigned buf_cnt;
1550 const uint8_t *buffer = xscale_debug_handler;
1551 int retval;
1552
1553 /* release SRST */
1554 jtag_add_reset(0, 0);
1555
1556 /* wait 300ms; 150 and 100ms were not enough */
1557 jtag_add_sleep(300*1000);
1558
1559 jtag_add_runtest(2030, TAP_IDLE);
1560 jtag_execute_queue();
1561
1562 /* set Hold reset, Halt mode and Trap Reset */
1563 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1564 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1565 xscale_write_dcsr(target, 1, 0);
1566
1567 /* Load the debug handler into the mini-icache. Since
1568 * it's using halt mode (not monitor mode), it runs in
1569 * "Special Debug State" for access to registers, memory,
1570 * coprocessors, trace data, etc.
1571 */
1572 address = xscale->handler_address;
1573 for (unsigned binary_size = sizeof xscale_debug_handler - 1;
1574 binary_size > 0;
1575 binary_size -= buf_cnt, buffer += buf_cnt)
1576 {
1577 uint32_t cache_line[8];
1578 unsigned i;
1579
1580 buf_cnt = binary_size;
1581 if (buf_cnt > 32)
1582 buf_cnt = 32;
1583
1584 for (i = 0; i < buf_cnt; i += 4)
1585 {
1586 /* convert LE buffer to host-endian uint32_t */
1587 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1588 }
1589
1590 for (; i < 32; i += 4)
1591 {
1592 cache_line[i / 4] = 0xe1a08008;
1593 }
1594
1595 /* only load addresses other than the reset vectors */
1596 if ((address % 0x400) != 0x0)
1597 {
1598 retval = xscale_load_ic(target, address,
1599 cache_line);
1600 if (retval != ERROR_OK)
1601 return retval;
1602 }
1603
1604 address += buf_cnt;
1605 };
1606
1607 retval = xscale_load_ic(target, 0x0,
1608 xscale->low_vectors);
1609 if (retval != ERROR_OK)
1610 return retval;
1611 retval = xscale_load_ic(target, 0xffff0000,
1612 xscale->high_vectors);
1613 if (retval != ERROR_OK)
1614 return retval;
1615
1616 jtag_add_runtest(30, TAP_IDLE);
1617
1618 jtag_add_sleep(100000);
1619
1620 /* set Hold reset, Halt mode and Trap Reset */
1621 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1622 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1623 xscale_write_dcsr(target, 1, 0);
1624
1625 /* clear Hold reset to let the target run (should enter debug handler) */
1626 xscale_write_dcsr(target, 0, 1);
1627 target->state = TARGET_RUNNING;
1628
1629 if (!target->reset_halt)
1630 {
1631 jtag_add_sleep(10000);
1632
1633 /* we should have entered debug now */
1634 xscale_debug_entry(target);
1635 target->state = TARGET_HALTED;
1636
1637 /* resume the target */
1638 xscale_resume(target, 1, 0x0, 1, 0);
1639 }
1640 }
1641
1642 return ERROR_OK;
1643 }
1644
1645 static int xscale_read_core_reg(struct target *target, struct reg *r,
1646 int num, enum arm_mode mode)
1647 {
1648 /** \todo add debug handler support for core register reads */
1649 LOG_ERROR("not implemented");
1650 return ERROR_OK;
1651 }
1652
1653 static int xscale_write_core_reg(struct target *target, struct reg *r,
1654 int num, enum arm_mode mode, uint32_t value)
1655 {
1656 /** \todo add debug handler support for core register writes */
1657 LOG_ERROR("not implemented");
1658 return ERROR_OK;
1659 }
1660
1661 static int xscale_full_context(struct target *target)
1662 {
1663 struct arm *armv4_5 = target_to_arm(target);
1664
1665 uint32_t *buffer;
1666
1667 int i, j;
1668
1669 LOG_DEBUG("-");
1670
1671 if (target->state != TARGET_HALTED)
1672 {
1673 LOG_WARNING("target not halted");
1674 return ERROR_TARGET_NOT_HALTED;
1675 }
1676
1677 buffer = malloc(4 * 8);
1678
1679 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1680 * we can't enter User mode on an XScale (unpredictable),
1681 * but User shares registers with SYS
1682 */
1683 for (i = 1; i < 7; i++)
1684 {
1685 enum arm_mode mode = armv4_5_number_to_mode(i);
1686 bool valid = true;
1687 struct reg *r;
1688
1689 if (mode == ARM_MODE_USR)
1690 continue;
1691
1692 /* check if there are invalid registers in the current mode
1693 */
1694 for (j = 0; valid && j <= 16; j++)
1695 {
1696 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1697 mode, j).valid)
1698 valid = false;
1699 }
1700 if (valid)
1701 continue;
1702
1703 /* request banked registers */
1704 xscale_send_u32(target, 0x0);
1705
1706 /* send CPSR for desired bank mode */
1707 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1708
1709 /* get banked registers: r8 to r14; and SPSR
1710 * except in USR/SYS mode
1711 */
1712 if (mode != ARM_MODE_SYS) {
1713 /* SPSR */
1714 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1715 mode, 16);
1716
1717 xscale_receive(target, buffer, 8);
1718
1719 buf_set_u32(r->value, 0, 32, buffer[7]);
1720 r->dirty = false;
1721 r->valid = true;
1722 } else {
1723 xscale_receive(target, buffer, 7);
1724 }
1725
1726 /* move data from buffer to register cache */
1727 for (j = 8; j <= 14; j++)
1728 {
1729 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1730 mode, j);
1731
1732 buf_set_u32(r->value, 0, 32, buffer[j - 8]);
1733 r->dirty = false;
1734 r->valid = true;
1735 }
1736 }
1737
1738 free(buffer);
1739
1740 return ERROR_OK;
1741 }
1742
1743 static int xscale_restore_banked(struct target *target)
1744 {
1745 struct arm *armv4_5 = target_to_arm(target);
1746
1747 int i, j;
1748
1749 if (target->state != TARGET_HALTED)
1750 {
1751 LOG_WARNING("target not halted");
1752 return ERROR_TARGET_NOT_HALTED;
1753 }
1754
1755 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1756 * and check if any banked registers need to be written. Ignore
1757 * USR mode (number 0) in favor of SYS; we can't enter User mode on
1758 * an XScale (unpredictable), but they share all registers.
1759 */
1760 for (i = 1; i < 7; i++)
1761 {
1762 enum arm_mode mode = armv4_5_number_to_mode(i);
1763 struct reg *r;
1764
1765 if (mode == ARM_MODE_USR)
1766 continue;
1767
1768 /* check if there are dirty registers in this mode */
1769 for (j = 8; j <= 14; j++)
1770 {
1771 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1772 mode, j).dirty)
1773 goto dirty;
1774 }
1775
1776 /* if not USR/SYS, check if the SPSR needs to be written */
1777 if (mode != ARM_MODE_SYS)
1778 {
1779 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1780 mode, 16).dirty)
1781 goto dirty;
1782 }
1783
1784 /* there's nothing to flush for this mode */
1785 continue;
1786
1787 dirty:
1788 /* command 0x1: "send banked registers" */
1789 xscale_send_u32(target, 0x1);
1790
1791 /* send CPSR for desired mode */
1792 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1793
1794 /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
1795 * but this protocol doesn't understand that nuance.
1796 */
1797 for (j = 8; j <= 14; j++) {
1798 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1799 mode, j);
1800 xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1801 r->dirty = false;
1802 }
1803
1804 /* send spsr if not in USR/SYS mode */
1805 if (mode != ARM_MODE_SYS) {
1806 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1807 mode, 16);
1808 xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1809 r->dirty = false;
1810 }
1811 }
1812
1813 return ERROR_OK;
1814 }
1815
1816 static int xscale_read_memory(struct target *target, uint32_t address,
1817 uint32_t size, uint32_t count, uint8_t *buffer)
1818 {
1819 struct xscale_common *xscale = target_to_xscale(target);
1820 uint32_t *buf32;
1821 uint32_t i;
1822 int retval;
1823
1824 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1825
1826 if (target->state != TARGET_HALTED)
1827 {
1828 LOG_WARNING("target not halted");
1829 return ERROR_TARGET_NOT_HALTED;
1830 }
1831
1832 /* sanitize arguments */
1833 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1834 return ERROR_INVALID_ARGUMENTS;
1835
1836 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1837 return ERROR_TARGET_UNALIGNED_ACCESS;
1838
1839 /* send memory read request (command 0x1n, n: access size) */
1840 if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
1841 return retval;
1842
1843 /* send base address for read request */
1844 if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1845 return retval;
1846
1847 /* send number of requested data words */
1848 if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1849 return retval;
1850
1851 /* receive data from target (count times 32-bit words in host endianness) */
1852 buf32 = malloc(4 * count);
1853 if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK)
1854 return retval;
1855
1856 /* extract data from host-endian buffer into byte stream */
1857 for (i = 0; i < count; i++)
1858 {
1859 switch (size)
1860 {
1861 case 4:
1862 target_buffer_set_u32(target, buffer, buf32[i]);
1863 buffer += 4;
1864 break;
1865 case 2:
1866 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1867 buffer += 2;
1868 break;
1869 case 1:
1870 *buffer++ = buf32[i] & 0xff;
1871 break;
1872 default:
1873 LOG_ERROR("invalid read size");
1874 return ERROR_INVALID_ARGUMENTS;
1875 }
1876 }
1877
1878 free(buf32);
1879
1880 /* examine DCSR, to see if Sticky Abort (SA) got set */
1881 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1882 return retval;
1883 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1884 {
1885 /* clear SA bit */
1886 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1887 return retval;
1888
1889 return ERROR_TARGET_DATA_ABORT;
1890 }
1891
1892 return ERROR_OK;
1893 }
1894
1895 static int xscale_read_phys_memory(struct target *target, uint32_t address,
1896 uint32_t size, uint32_t count, uint8_t *buffer)
1897 {
1898 struct xscale_common *xscale = target_to_xscale(target);
1899
1900 /* with MMU inactive, there are only physical addresses */
1901 if (!xscale->armv4_5_mmu.mmu_enabled)
1902 return xscale_read_memory(target, address, size, count, buffer);
1903
1904 /** \todo: provide a non-stub implementation of this routine. */
1905 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1906 target_name(target), __func__);
1907 return ERROR_FAIL;
1908 }
1909
1910 static int xscale_write_memory(struct target *target, uint32_t address,
1911 uint32_t size, uint32_t count, uint8_t *buffer)
1912 {
1913 struct xscale_common *xscale = target_to_xscale(target);
1914 int retval;
1915
1916 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1917
1918 if (target->state != TARGET_HALTED)
1919 {
1920 LOG_WARNING("target not halted");
1921 return ERROR_TARGET_NOT_HALTED;
1922 }
1923
1924 /* sanitize arguments */
1925 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1926 return ERROR_INVALID_ARGUMENTS;
1927
1928 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1929 return ERROR_TARGET_UNALIGNED_ACCESS;
1930
1931 /* send memory write request (command 0x2n, n: access size) */
1932 if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
1933 return retval;
1934
1935 /* send base address for read request */
1936 if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1937 return retval;
1938
1939 /* send number of requested data words to be written*/
1940 if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1941 return retval;
1942
1943 /* extract data from host-endian buffer into byte stream */
1944 #if 0
1945 for (i = 0; i < count; i++)
1946 {
1947 switch (size)
1948 {
1949 case 4:
1950 value = target_buffer_get_u32(target, buffer);
1951 xscale_send_u32(target, value);
1952 buffer += 4;
1953 break;
1954 case 2:
1955 value = target_buffer_get_u16(target, buffer);
1956 xscale_send_u32(target, value);
1957 buffer += 2;
1958 break;
1959 case 1:
1960 value = *buffer;
1961 xscale_send_u32(target, value);
1962 buffer += 1;
1963 break;
1964 default:
1965 LOG_ERROR("should never get here");
1966 exit(-1);
1967 }
1968 }
1969 #endif
1970 if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK)
1971 return retval;
1972
1973 /* examine DCSR, to see if Sticky Abort (SA) got set */
1974 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1975 return retval;
1976 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1977 {
1978 /* clear SA bit */
1979 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1980 return retval;
1981
1982 LOG_ERROR("data abort writing memory");
1983 return ERROR_TARGET_DATA_ABORT;
1984 }
1985
1986 return ERROR_OK;
1987 }
1988
1989 static int xscale_write_phys_memory(struct target *target, uint32_t address,
1990 uint32_t size, uint32_t count, uint8_t *buffer)
1991 {
1992 struct xscale_common *xscale = target_to_xscale(target);
1993
1994 /* with MMU inactive, there are only physical addresses */
1995 if (!xscale->armv4_5_mmu.mmu_enabled)
1996 return xscale_read_memory(target, address, size, count, buffer);
1997
1998 /** \todo: provide a non-stub implementation of this routine. */
1999 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
2000 target_name(target), __func__);
2001 return ERROR_FAIL;
2002 }
2003
2004 static int xscale_bulk_write_memory(struct target *target, uint32_t address,
2005 uint32_t count, uint8_t *buffer)
2006 {
2007 return xscale_write_memory(target, address, 4, count, buffer);
2008 }
2009
2010 static int xscale_get_ttb(struct target *target, uint32_t *result)
2011 {
2012 struct xscale_common *xscale = target_to_xscale(target);
2013 uint32_t ttb;
2014 int retval;
2015
2016 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2017 if (retval != ERROR_OK)
2018 return retval;
2019 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2020
2021 *result = ttb;
2022
2023 return ERROR_OK;
2024 }
2025
2026 static int xscale_disable_mmu_caches(struct target *target, int mmu,
2027 int d_u_cache, int i_cache)
2028 {
2029 struct xscale_common *xscale = target_to_xscale(target);
2030 uint32_t cp15_control;
2031 int retval;
2032
2033 /* read cp15 control register */
2034 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2035 if (retval !=ERROR_OK)
2036 return retval;
2037 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2038
2039 if (mmu)
2040 cp15_control &= ~0x1U;
2041
2042 if (d_u_cache)
2043 {
2044 /* clean DCache */
2045 retval = xscale_send_u32(target, 0x50);
2046 if (retval !=ERROR_OK)
2047 return retval;
2048 retval = xscale_send_u32(target, xscale->cache_clean_address);
2049 if (retval !=ERROR_OK)
2050 return retval;
2051
2052 /* invalidate DCache */
2053 retval = xscale_send_u32(target, 0x51);
2054 if (retval !=ERROR_OK)
2055 return retval;
2056
2057 cp15_control &= ~0x4U;
2058 }
2059
2060 if (i_cache)
2061 {
2062 /* invalidate ICache */
2063 retval = xscale_send_u32(target, 0x52);
2064 if (retval !=ERROR_OK)
2065 return retval;
2066 cp15_control &= ~0x1000U;
2067 }
2068
2069 /* write new cp15 control register */
2070 retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2071 if (retval !=ERROR_OK)
2072 return retval;
2073
2074 /* execute cpwait to ensure outstanding operations complete */
2075 retval = xscale_send_u32(target, 0x53);
2076 return retval;
2077 }
2078
2079 static int xscale_enable_mmu_caches(struct target *target, int mmu,
2080 int d_u_cache, int i_cache)
2081 {
2082 struct xscale_common *xscale = target_to_xscale(target);
2083 uint32_t cp15_control;
2084 int retval;
2085
2086 /* read cp15 control register */
2087 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2088 if (retval !=ERROR_OK)
2089 return retval;
2090 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2091
2092 if (mmu)
2093 cp15_control |= 0x1U;
2094
2095 if (d_u_cache)
2096 cp15_control |= 0x4U;
2097
2098 if (i_cache)
2099 cp15_control |= 0x1000U;
2100
2101 /* write new cp15 control register */
2102 retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2103 if (retval !=ERROR_OK)
2104 return retval;
2105
2106 /* execute cpwait to ensure outstanding operations complete */
2107 retval = xscale_send_u32(target, 0x53);
2108 return retval;
2109 }
2110
2111 static int xscale_set_breakpoint(struct target *target,
2112 struct breakpoint *breakpoint)
2113 {
2114 int retval;
2115 struct xscale_common *xscale = target_to_xscale(target);
2116
2117 if (target->state != TARGET_HALTED)
2118 {
2119 LOG_WARNING("target not halted");
2120 return ERROR_TARGET_NOT_HALTED;
2121 }
2122
2123 if (breakpoint->set)
2124 {
2125 LOG_WARNING("breakpoint already set");
2126 return ERROR_OK;
2127 }
2128
2129 if (breakpoint->type == BKPT_HARD)
2130 {
2131 uint32_t value = breakpoint->address | 1;
2132 if (!xscale->ibcr0_used)
2133 {
2134 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2135 xscale->ibcr0_used = 1;
2136 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2137 }
2138 else if (!xscale->ibcr1_used)
2139 {
2140 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2141 xscale->ibcr1_used = 1;
2142 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2143 }
2144 else
2145 { /* bug: availability previously verified in xscale_add_breakpoint() */
2146 LOG_ERROR("BUG: no hardware comparator available");
2147 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2148 }
2149 }
2150 else if (breakpoint->type == BKPT_SOFT)
2151 {
2152 if (breakpoint->length == 4)
2153 {
2154 /* keep the original instruction in target endianness */
2155 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2156 {
2157 return retval;
2158 }
2159 /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2160 if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
2161 {
2162 return retval;
2163 }
2164 }
2165 else
2166 {
2167 /* keep the original instruction in target endianness */
2168 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2169 {
2170 return retval;
2171 }
2172 /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2173 if ((retval = target_write_u16(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
2174 {
2175 return retval;
2176 }
2177 }
2178 breakpoint->set = 1;
2179
2180 xscale_send_u32(target, 0x50); /* clean dcache */
2181 xscale_send_u32(target, xscale->cache_clean_address);
2182 xscale_send_u32(target, 0x51); /* invalidate dcache */
2183 xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
2184 }
2185
2186 return ERROR_OK;
2187 }
2188
2189 static int xscale_add_breakpoint(struct target *target,
2190 struct breakpoint *breakpoint)
2191 {
2192 struct xscale_common *xscale = target_to_xscale(target);
2193
2194 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2195 {
2196 LOG_ERROR("no breakpoint unit available for hardware breakpoint");
2197 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2198 }
2199
2200 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2201 {
2202 LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2203 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2204 }
2205
2206 if (breakpoint->type == BKPT_HARD)
2207 {
2208 xscale->ibcr_available--;
2209 }
2210
2211 return xscale_set_breakpoint(target, breakpoint);
2212 }
2213
2214 static int xscale_unset_breakpoint(struct target *target,
2215 struct breakpoint *breakpoint)
2216 {
2217 int retval;
2218 struct xscale_common *xscale = target_to_xscale(target);
2219
2220 if (target->state != TARGET_HALTED)
2221 {
2222 LOG_WARNING("target not halted");
2223 return ERROR_TARGET_NOT_HALTED;
2224 }
2225
2226 if (!breakpoint->set)
2227 {
2228 LOG_WARNING("breakpoint not set");
2229 return ERROR_OK;
2230 }
2231
2232 if (breakpoint->type == BKPT_HARD)
2233 {
2234 if (breakpoint->set == 1)
2235 {
2236 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2237 xscale->ibcr0_used = 0;
2238 }
2239 else if (breakpoint->set == 2)
2240 {
2241 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2242 xscale->ibcr1_used = 0;
2243 }
2244 breakpoint->set = 0;
2245 }
2246 else
2247 {
2248 /* restore original instruction (kept in target endianness) */
2249 if (breakpoint->length == 4)
2250 {
2251 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2252 {
2253 return retval;
2254 }
2255 }
2256 else
2257 {
2258 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2259 {
2260 return retval;
2261 }
2262 }
2263 breakpoint->set = 0;
2264
2265 xscale_send_u32(target, 0x50); /* clean dcache */
2266 xscale_send_u32(target, xscale->cache_clean_address);
2267 xscale_send_u32(target, 0x51); /* invalidate dcache */
2268 xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
2269 }
2270
2271 return ERROR_OK;
2272 }
2273
2274 static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2275 {
2276 struct xscale_common *xscale = target_to_xscale(target);
2277
2278 if (target->state != TARGET_HALTED)
2279 {
2280 LOG_ERROR("target not halted");
2281 return ERROR_TARGET_NOT_HALTED;
2282 }
2283
2284 if (breakpoint->set)
2285 {
2286 xscale_unset_breakpoint(target, breakpoint);
2287 }
2288
2289 if (breakpoint->type == BKPT_HARD)
2290 xscale->ibcr_available++;
2291
2292 return ERROR_OK;
2293 }
2294
2295 static int xscale_set_watchpoint(struct target *target,
2296 struct watchpoint *watchpoint)
2297 {
2298 struct xscale_common *xscale = target_to_xscale(target);
2299 uint32_t enable = 0;
2300 struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2301 uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2302
2303 if (target->state != TARGET_HALTED)
2304 {
2305 LOG_ERROR("target not halted");
2306 return ERROR_TARGET_NOT_HALTED;
2307 }
2308
2309 switch (watchpoint->rw)
2310 {
2311 case WPT_READ:
2312 enable = 0x3;
2313 break;
2314 case WPT_ACCESS:
2315 enable = 0x2;
2316 break;
2317 case WPT_WRITE:
2318 enable = 0x1;
2319 break;
2320 default:
2321 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2322 }
2323
2324 /* For watchpoint across more than one word, both DBR registers must
2325 be enlisted, with the second used as a mask. */
2326 if (watchpoint->length > 4)
2327 {
2328 if (xscale->dbr0_used || xscale->dbr1_used)
2329 {
2330 LOG_ERROR("BUG: sufficient hardware comparators unavailable");
2331 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2332 }
2333
2334 /* Write mask value to DBR1, based on the length argument.
2335 * Address bits ignored by the comparator are those set in mask. */
2336 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
2337 watchpoint->length - 1);
2338 xscale->dbr1_used = 1;
2339 enable |= 0x100; /* DBCON[M] */
2340 }
2341
2342 if (!xscale->dbr0_used)
2343 {
2344 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2345 dbcon_value |= enable;
2346 xscale_set_reg_u32(dbcon, dbcon_value);
2347 watchpoint->set = 1;
2348 xscale->dbr0_used = 1;
2349 }
2350 else if (!xscale->dbr1_used)
2351 {
2352 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2353 dbcon_value |= enable << 2;
2354 xscale_set_reg_u32(dbcon, dbcon_value);
2355 watchpoint->set = 2;
2356 xscale->dbr1_used = 1;
2357 }
2358 else
2359 {
2360 LOG_ERROR("BUG: no hardware comparator available");
2361 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2362 }
2363
2364 return ERROR_OK;
2365 }
2366
2367 static int xscale_add_watchpoint(struct target *target,
2368 struct watchpoint *watchpoint)
2369 {
2370 struct xscale_common *xscale = target_to_xscale(target);
2371
2372 if (xscale->dbr_available < 1)
2373 {
2374 LOG_ERROR("no more watchpoint registers available");
2375 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2376 }
2377
2378 if (watchpoint->value)
2379 LOG_WARNING("xscale does not support value, mask arguments; ignoring");
2380
2381 /* check that length is a power of two */
2382 for (uint32_t len = watchpoint->length; len != 1; len /= 2)
2383 {
2384 if (len % 2)
2385 {
2386 LOG_ERROR("xscale requires that watchpoint length is a power of two");
2387 return ERROR_COMMAND_ARGUMENT_INVALID;
2388 }
2389 }
2390
2391 if (watchpoint->length == 4) /* single word watchpoint */
2392 {
2393 xscale->dbr_available--; /* one DBR reg used */
2394 return ERROR_OK;
2395 }
2396
2397 /* watchpoints across multiple words require both DBR registers */
2398 if (xscale->dbr_available < 2)
2399 {
2400 LOG_ERROR("insufficient watchpoint registers available");
2401 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2402 }
2403
2404 xscale->dbr_available = 0;
2405 return ERROR_OK;
2406 }
2407
2408 static int xscale_unset_watchpoint(struct target *target,
2409 struct watchpoint *watchpoint)
2410 {
2411 struct xscale_common *xscale = target_to_xscale(target);
2412 struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2413 uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2414
2415 if (target->state != TARGET_HALTED)
2416 {
2417 LOG_WARNING("target not halted");
2418 return ERROR_TARGET_NOT_HALTED;
2419 }
2420
2421 if (!watchpoint->set)
2422 {
2423 LOG_WARNING("breakpoint not set");
2424 return ERROR_OK;
2425 }
2426
2427 if (watchpoint->set == 1)
2428 {
2429 if (watchpoint->length > 4)
2430 {
2431 dbcon_value &= ~0x103; /* clear DBCON[M] as well */
2432 xscale->dbr1_used = 0; /* DBR1 was used for mask */
2433 }
2434 else
2435 dbcon_value &= ~0x3;
2436
2437 xscale_set_reg_u32(dbcon, dbcon_value);
2438 xscale->dbr0_used = 0;
2439 }
2440 else if (watchpoint->set == 2)
2441 {
2442 dbcon_value &= ~0xc;
2443 xscale_set_reg_u32(dbcon, dbcon_value);
2444 xscale->dbr1_used = 0;
2445 }
2446 watchpoint->set = 0;
2447
2448 return ERROR_OK;
2449 }
2450
2451 static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
2452 {
2453 struct xscale_common *xscale = target_to_xscale(target);
2454
2455 if (target->state != TARGET_HALTED)
2456 {
2457 LOG_ERROR("target not halted");
2458 return ERROR_TARGET_NOT_HALTED;
2459 }
2460
2461 if (watchpoint->set)
2462 {
2463 xscale_unset_watchpoint(target, watchpoint);
2464 }
2465
2466 if (watchpoint->length > 4)
2467 xscale->dbr_available++; /* both DBR regs now available */
2468
2469 xscale->dbr_available++;
2470
2471 return ERROR_OK;
2472 }
2473
2474 static int xscale_get_reg(struct reg *reg)
2475 {
2476 struct xscale_reg *arch_info = reg->arch_info;
2477 struct target *target = arch_info->target;
2478 struct xscale_common *xscale = target_to_xscale(target);
2479
2480 /* DCSR, TX and RX are accessible via JTAG */
2481 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2482 {
2483 return xscale_read_dcsr(arch_info->target);
2484 }
2485 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2486 {
2487 /* 1 = consume register content */
2488 return xscale_read_tx(arch_info->target, 1);
2489 }
2490 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2491 {
2492 /* can't read from RX register (host -> debug handler) */
2493 return ERROR_OK;
2494 }
2495 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2496 {
2497 /* can't (explicitly) read from TXRXCTRL register */
2498 return ERROR_OK;
2499 }
2500 else /* Other DBG registers have to be transfered by the debug handler */
2501 {
2502 /* send CP read request (command 0x40) */
2503 xscale_send_u32(target, 0x40);
2504
2505 /* send CP register number */
2506 xscale_send_u32(target, arch_info->dbg_handler_number);
2507
2508 /* read register value */
2509 xscale_read_tx(target, 1);
2510 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2511
2512 reg->dirty = 0;
2513 reg->valid = 1;
2514 }
2515
2516 return ERROR_OK;
2517 }
2518
2519 static int xscale_set_reg(struct reg *reg, uint8_t* buf)
2520 {
2521 struct xscale_reg *arch_info = reg->arch_info;
2522 struct target *target = arch_info->target;
2523 struct xscale_common *xscale = target_to_xscale(target);
2524 uint32_t value = buf_get_u32(buf, 0, 32);
2525
2526 /* DCSR, TX and RX are accessible via JTAG */
2527 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2528 {
2529 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2530 return xscale_write_dcsr(arch_info->target, -1, -1);
2531 }
2532 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2533 {
2534 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2535 return xscale_write_rx(arch_info->target);
2536 }
2537 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2538 {
2539 /* can't write to TX register (debug-handler -> host) */
2540 return ERROR_OK;
2541 }
2542 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2543 {
2544 /* can't (explicitly) write to TXRXCTRL register */
2545 return ERROR_OK;
2546 }
2547 else /* Other DBG registers have to be transfered by the debug handler */
2548 {
2549 /* send CP write request (command 0x41) */
2550 xscale_send_u32(target, 0x41);
2551
2552 /* send CP register number */
2553 xscale_send_u32(target, arch_info->dbg_handler_number);
2554
2555 /* send CP register value */
2556 xscale_send_u32(target, value);
2557 buf_set_u32(reg->value, 0, 32, value);
2558 }
2559
2560 return ERROR_OK;
2561 }
2562
2563 static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
2564 {
2565 struct xscale_common *xscale = target_to_xscale(target);
2566 struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2567 struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
2568
2569 /* send CP write request (command 0x41) */
2570 xscale_send_u32(target, 0x41);
2571
2572 /* send CP register number */
2573 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2574
2575 /* send CP register value */
2576 xscale_send_u32(target, value);
2577 buf_set_u32(dcsr->value, 0, 32, value);
2578
2579 return ERROR_OK;
2580 }
2581
2582 static int xscale_read_trace(struct target *target)
2583 {
2584 struct xscale_common *xscale = target_to_xscale(target);
2585 struct arm *armv4_5 = &xscale->armv4_5_common;
2586 struct xscale_trace_data **trace_data_p;
2587
2588 /* 258 words from debug handler
2589 * 256 trace buffer entries
2590 * 2 checkpoint addresses
2591 */
2592 uint32_t trace_buffer[258];
2593 int is_address[256];
2594 int i, j;
2595 unsigned int num_checkpoints = 0;
2596
2597 if (target->state != TARGET_HALTED)
2598 {
2599 LOG_WARNING("target must be stopped to read trace data");
2600 return ERROR_TARGET_NOT_HALTED;
2601 }
2602
2603 /* send read trace buffer command (command 0x61) */
2604 xscale_send_u32(target, 0x61);
2605
2606 /* receive trace buffer content */
2607 xscale_receive(target, trace_buffer, 258);
2608
2609 /* parse buffer backwards to identify address entries */
2610 for (i = 255; i >= 0; i--)
2611 {
2612 /* also count number of checkpointed entries */
2613 if ((trace_buffer[i] & 0xe0) == 0xc0)
2614 num_checkpoints++;
2615
2616 is_address[i] = 0;
2617 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2618 ((trace_buffer[i] & 0xf0) == 0xd0))
2619 {
2620 if (i > 0)
2621 is_address[--i] = 1;
2622 if (i > 0)
2623 is_address[--i] = 1;
2624 if (i > 0)
2625 is_address[--i] = 1;
2626 if (i > 0)
2627 is_address[--i] = 1;
2628 }
2629 }
2630
2631
2632 /* search first non-zero entry that is not part of an address */
2633 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2634 ;
2635
2636 if (j == 256)
2637 {
2638 LOG_DEBUG("no trace data collected");
2639 return ERROR_XSCALE_NO_TRACE_DATA;
2640 }
2641
2642 /* account for possible partial address at buffer start (wrap mode only) */
2643 if (is_address[0])
2644 { /* first entry is address; complete set of 4? */
2645 i = 1;
2646 while (i < 4)
2647 if (!is_address[i++])
2648 break;
2649 if (i < 4)
2650 j += i; /* partial address; can't use it */
2651 }
2652
2653 /* if first valid entry is indirect branch, can't use that either (no address) */
2654 if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
2655 j++;
2656
2657 /* walk linked list to terminating entry */
2658 for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2659 ;
2660
2661 *trace_data_p = malloc(sizeof(struct xscale_trace_data));
2662 (*trace_data_p)->next = NULL;
2663 (*trace_data_p)->chkpt0 = trace_buffer[256];
2664 (*trace_data_p)->chkpt1 = trace_buffer[257];
2665 (*trace_data_p)->last_instruction =
2666 buf_get_u32(armv4_5->pc->value, 0, 32);
2667 (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
2668 (*trace_data_p)->depth = 256 - j;
2669 (*trace_data_p)->num_checkpoints = num_checkpoints;
2670
2671 for (i = j; i < 256; i++)
2672 {
2673 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2674 if (is_address[i])
2675 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2676 else
2677 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2678 }
2679
2680 return ERROR_OK;
2681 }
2682
2683 static int xscale_read_instruction(struct target *target, uint32_t pc,
2684 struct arm_instruction *instruction)
2685 {
2686 struct xscale_common *const xscale = target_to_xscale(target);
2687 int i;
2688 int section = -1;
2689 size_t size_read;
2690 uint32_t opcode;
2691 int retval;
2692
2693 if (!xscale->trace.image)
2694 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2695
2696 /* search for the section the current instruction belongs to */
2697 for (i = 0; i < xscale->trace.image->num_sections; i++)
2698 {
2699 if ((xscale->trace.image->sections[i].base_address <= pc) &&
2700 (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > pc))
2701 {
2702 section = i;
2703 break;
2704 }
2705 }
2706
2707 if (section == -1)
2708 {
2709 /* current instruction couldn't be found in the image */
2710 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2711 }
2712
2713 if (xscale->trace.core_state == ARM_STATE_ARM)
2714 {
2715 uint8_t buf[4];
2716 if ((retval = image_read_section(xscale->trace.image, section,
2717 pc - xscale->trace.image->sections[section].base_address,
2718 4, buf, &size_read)) != ERROR_OK)
2719 {
2720 LOG_ERROR("error while reading instruction: %i", retval);
2721 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2722 }
2723 opcode = target_buffer_get_u32(target, buf);
2724 arm_evaluate_opcode(opcode, pc, instruction);
2725 }
2726 else if (xscale->trace.core_state == ARM_STATE_THUMB)
2727 {
2728 uint8_t buf[2];
2729 if ((retval = image_read_section(xscale->trace.image, section,
2730 pc - xscale->trace.image->sections[section].base_address,
2731 2, buf, &size_read)) != ERROR_OK)
2732 {
2733 LOG_ERROR("error while reading instruction: %i", retval);
2734 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2735 }
2736 opcode = target_buffer_get_u16(target, buf);
2737 thumb_evaluate_opcode(opcode, pc, instruction);
2738 }
2739 else
2740 {
2741 LOG_ERROR("BUG: unknown core state encountered");
2742 exit(-1);
2743 }
2744
2745 return ERROR_OK;
2746 }
2747
2748 /* Extract address encoded into trace data.
2749 * Write result to address referenced by argument 'target', or 0 if incomplete. */
2750 static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
2751 int i, uint32_t *target)
2752 {
2753 /* if there are less than four entries prior to the indirect branch message
2754 * we can't extract the address */
2755 if (i < 4)
2756 *target = 0;
2757 else
2758 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2759 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2760 }
2761
2762 static inline void xscale_display_instruction(struct target *target, uint32_t pc,
2763 struct arm_instruction *instruction,
2764 struct command_context *cmd_ctx)
2765 {
2766 int retval = xscale_read_instruction(target, pc, instruction);
2767 if (retval == ERROR_OK)
2768 command_print(cmd_ctx, "%s", instruction->text);
2769 else
2770 command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc);
2771 }
2772
2773 static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
2774 {
2775 struct xscale_common *xscale = target_to_xscale(target);
2776 struct xscale_trace_data *trace_data = xscale->trace.data;
2777 int i, retval;
2778 uint32_t breakpoint_pc;
2779 struct arm_instruction instruction;
2780 uint32_t current_pc = 0; /* initialized when address determined */
2781
2782 if (!xscale->trace.image)
2783 LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
2784
2785 /* loop for each trace buffer that was loaded from target */
2786 while (trace_data)
2787 {
2788 int chkpt = 0; /* incremented as checkpointed entries found */
2789 int j;
2790
2791 /* FIXME: set this to correct mode when trace buffer is first enabled */
2792 xscale->trace.core_state = ARM_STATE_ARM;
2793
2794 /* loop for each entry in this trace buffer */
2795 for (i = 0; i < trace_data->depth; i++)
2796 {
2797 int exception = 0;
2798 uint32_t chkpt_reg = 0x0;
2799 uint32_t branch_target = 0;
2800 int count;
2801
2802 /* trace entry type is upper nybble of 'message byte' */
2803 int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4;
2804
2805 /* Target addresses of indirect branches are written into buffer
2806 * before the message byte representing the branch. Skip past it */
2807 if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2808 continue;
2809
2810 switch (trace_msg_type)
2811 {
2812 case 0: /* Exceptions */
2813 case 1:
2814 case 2:
2815 case 3:
2816 case 4:
2817 case 5:
2818 case 6:
2819 case 7:
2820 exception = (trace_data->entries[i].data & 0x70) >> 4;
2821
2822 /* FIXME: vector table may be at ffff0000 */
2823 branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
2824 break;
2825
2826 case 8: /* Direct Branch */
2827 break;
2828
2829 case 9: /* Indirect Branch */
2830 xscale_branch_address(trace_data, i, &branch_target);
2831 break;
2832
2833 case 13: /* Checkpointed Indirect Branch */
2834 xscale_branch_address(trace_data, i, &branch_target);
2835 if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2836 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */
2837 else
2838 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */
2839
2840 chkpt++;
2841 break;
2842
2843 case 12: /* Checkpointed Direct Branch */
2844 if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2845 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */
2846 else
2847 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */
2848
2849 /* if no current_pc, checkpoint will be starting point */
2850 if (current_pc == 0)
2851 branch_target = chkpt_reg;
2852
2853 chkpt++;
2854 break;
2855
2856 case 15: /* Roll-over */
2857 break;
2858
2859 default: /* Reserved */
2860 LOG_WARNING("trace is suspect: invalid trace message byte");
2861 continue;
2862
2863 }
2864
2865 /* If we don't have the current_pc yet, but we did get the branch target
2866 * (either from the trace buffer on indirect branch, or from a checkpoint reg),
2867 * then we can start displaying instructions at the next iteration, with
2868 * branch_target as the starting point.
2869 */
2870 if (current_pc == 0)
2871 {
2872 current_pc = branch_target; /* remains 0 unless branch_target obtained */
2873 continue;
2874 }
2875
2876 /* We have current_pc. Read and display the instructions from the image.
2877 * First, display count instructions (lower nybble of message byte). */
2878 count = trace_data->entries[i].data & 0x0f;
2879 for (j = 0; j < count; j++)
2880 {
2881 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2882 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2883 }
2884
2885 /* An additional instruction is implicitly added to count for
2886 * rollover and some exceptions: undef, swi, prefetch abort. */
2887 if ((trace_msg_type == 15) || (exception > 0 && exception < 4))
2888 {
2889 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2890 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2891 }
2892
2893 if (trace_msg_type == 15) /* rollover */
2894 continue;
2895
2896 if (exception)
2897 {
2898 command_print(cmd_ctx, "--- exception %i ---", exception);
2899 continue;
2900 }
2901
2902 /* not exception or rollover; next instruction is a branch and is
2903 * not included in the count */
2904 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2905
2906 /* for direct branches, extract branch destination from instruction */
2907 if ((trace_msg_type == 8) || (trace_msg_type == 12))
2908 {
2909 retval = xscale_read_instruction(target, current_pc, &instruction);
2910 if (retval == ERROR_OK)
2911 current_pc = instruction.info.b_bl_bx_blx.target_address;
2912 else
2913 current_pc = 0; /* branch destination unknown */
2914
2915 /* direct branch w/ checkpoint; can also get from checkpoint reg */
2916 if (trace_msg_type == 12)
2917 {
2918 if (current_pc == 0)
2919 current_pc = chkpt_reg;
2920 else if (current_pc != chkpt_reg) /* sanity check */
2921 LOG_WARNING("trace is suspect: checkpoint register "
2922 "inconsistent with adddress from image");
2923 }
2924
2925 if (current_pc == 0)
2926 command_print(cmd_ctx, "address unknown");
2927
2928 continue;
2929 }
2930
2931 /* indirect branch; the branch destination was read from trace buffer */
2932 if ((trace_msg_type == 9) || (trace_msg_type == 13))
2933 {
2934 current_pc = branch_target;
2935
2936 /* sanity check (checkpoint reg is redundant) */
2937 if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
2938 LOG_WARNING("trace is suspect: checkpoint register "
2939 "inconsistent with address from trace buffer");
2940 }
2941
2942 } /* END: for (i = 0; i < trace_data->depth; i++) */
2943
2944 breakpoint_pc = trace_data->last_instruction; /* used below */
2945 trace_data = trace_data->next;
2946
2947 } /* END: while (trace_data) */
2948
2949 /* Finally... display all instructions up to the value of the pc when the
2950 * debug break occurred (saved when trace data was collected from target).
2951 * This is necessary because the trace only records execution branches and 16
2952 * consecutive instructions (rollovers), so last few typically missed.
2953 */
2954 if (current_pc == 0)
2955 return ERROR_OK; /* current_pc was never found */
2956
2957 /* how many instructions remaining? */
2958 int gap_count = (breakpoint_pc - current_pc) /
2959 (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
2960
2961 /* should never be negative or over 16, but verify */
2962 if (gap_count < 0 || gap_count > 16)
2963 {
2964 LOG_WARNING("trace is suspect: excessive gap at end of trace");
2965 return ERROR_OK; /* bail; large number or negative value no good */
2966 }
2967
2968 /* display remaining instructions */
2969 for (i = 0; i < gap_count; i++)
2970 {
2971 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2972 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2973 }
2974
2975 return ERROR_OK;
2976 }
2977
2978 static const struct reg_arch_type xscale_reg_type = {
2979 .get = xscale_get_reg,
2980 .set = xscale_set_reg,
2981 };
2982
2983 static void xscale_build_reg_cache(struct target *target)
2984 {
2985 struct xscale_common *xscale = target_to_xscale(target);
2986 struct arm *armv4_5 = &xscale->armv4_5_common;
2987 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
2988 struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
2989 int i;
2990 int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
2991
2992 (*cache_p) = arm_build_reg_cache(target, armv4_5);
2993
2994 (*cache_p)->next = malloc(sizeof(struct reg_cache));
2995 cache_p = &(*cache_p)->next;
2996
2997 /* fill in values for the xscale reg cache */
2998 (*cache_p)->name = "XScale registers";
2999 (*cache_p)->next = NULL;
3000 (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
3001 (*cache_p)->num_regs = num_regs;
3002
3003 for (i = 0; i < num_regs; i++)
3004 {
3005 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
3006 (*cache_p)->reg_list[i].value = calloc(4, 1);
3007 (*cache_p)->reg_list[i].dirty = 0;
3008 (*cache_p)->reg_list[i].valid = 0;
3009 (*cache_p)->reg_list[i].size = 32;
3010 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
3011 (*cache_p)->reg_list[i].type = &xscale_reg_type;
3012 arch_info[i] = xscale_reg_arch_info[i];
3013 arch_info[i].target = target;
3014 }
3015
3016 xscale->reg_cache = (*cache_p);
3017 }
3018
3019 static int xscale_init_target(struct command_context *cmd_ctx,
3020 struct target *target)
3021 {
3022 xscale_build_reg_cache(target);
3023 return ERROR_OK;
3024 }
3025
3026 static int xscale_init_arch_info(struct target *target,
3027 struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
3028 {
3029 struct arm *armv4_5;
3030 uint32_t high_reset_branch, low_reset_branch;
3031 int i;
3032
3033 armv4_5 = &xscale->armv4_5_common;
3034
3035 /* store architecture specfic data */
3036 xscale->common_magic = XSCALE_COMMON_MAGIC;
3037
3038 /* we don't really *need* a variant param ... */
3039 if (variant) {
3040 int ir_length = 0;
3041
3042 if (strcmp(variant, "pxa250") == 0
3043 || strcmp(variant, "pxa255") == 0
3044 || strcmp(variant, "pxa26x") == 0)
3045 ir_length = 5;
3046 else if (strcmp(variant, "pxa27x") == 0
3047 || strcmp(variant, "ixp42x") == 0
3048 || strcmp(variant, "ixp45x") == 0
3049 || strcmp(variant, "ixp46x") == 0)
3050 ir_length = 7;
3051 else if (strcmp(variant, "pxa3xx") == 0)
3052 ir_length = 11;
3053 else
3054 LOG_WARNING("%s: unrecognized variant %s",
3055 tap->dotted_name, variant);
3056
3057 if (ir_length && ir_length != tap->ir_length) {
3058 LOG_WARNING("%s: IR length for %s is %d; fixing",
3059 tap->dotted_name, variant, ir_length);
3060 tap->ir_length = ir_length;
3061 }
3062 }
3063
3064 /* PXA3xx shifts the JTAG instructions */
3065 if (tap->ir_length == 11)
3066 xscale->xscale_variant = XSCALE_PXA3XX;
3067 else
3068 xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
3069
3070 /* the debug handler isn't installed (and thus not running) at this time */
3071 xscale->handler_address = 0xfe000800;
3072
3073 /* clear the vectors we keep locally for reference */
3074 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
3075 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
3076
3077 /* no user-specified vectors have been configured yet */
3078 xscale->static_low_vectors_set = 0x0;
3079 xscale->static_high_vectors_set = 0x0;
3080
3081 /* calculate branches to debug handler */
3082 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
3083 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
3084
3085 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
3086 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
3087
3088 for (i = 1; i <= 7; i++)
3089 {
3090 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3091 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3092 }
3093
3094 /* 64kB aligned region used for DCache cleaning */
3095 xscale->cache_clean_address = 0xfffe0000;
3096
3097 xscale->hold_rst = 0;
3098 xscale->external_debug_break = 0;
3099
3100 xscale->ibcr_available = 2;
3101 xscale->ibcr0_used = 0;
3102 xscale->ibcr1_used = 0;
3103
3104 xscale->dbr_available = 2;
3105 xscale->dbr0_used = 0;
3106 xscale->dbr1_used = 0;
3107
3108 LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
3109 target_name(target));
3110
3111 xscale->arm_bkpt = ARMV5_BKPT(0x0);
3112 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
3113
3114 xscale->vector_catch = 0x1;
3115
3116 xscale->trace.capture_status = TRACE_IDLE;
3117 xscale->trace.data = NULL;
3118 xscale->trace.image = NULL;
3119 xscale->trace.buffer_enabled = 0;
3120 xscale->trace.buffer_fill = 0;
3121
3122 /* prepare ARMv4/5 specific information */
3123 armv4_5->arch_info = xscale;
3124 armv4_5->read_core_reg = xscale_read_core_reg;
3125 armv4_5->write_core_reg = xscale_write_core_reg;
3126 armv4_5->full_context = xscale_full_context;
3127
3128 arm_init_arch_info(target, armv4_5);
3129
3130 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3131 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3132 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3133 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3134 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3135 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3136 xscale->armv4_5_mmu.has_tiny_pages = 1;
3137 xscale->armv4_5_mmu.mmu_enabled = 0;
3138
3139 return ERROR_OK;
3140 }
3141
3142 static int xscale_target_create(struct target *target, Jim_Interp *interp)
3143 {
3144 struct xscale_common *xscale;
3145
3146 if (sizeof xscale_debug_handler - 1 > 0x800) {
3147 LOG_ERROR("debug_handler.bin: larger than 2kb");
3148 return ERROR_FAIL;
3149 }
3150
3151 xscale = calloc(1, sizeof(*xscale));
3152 if (!xscale)
3153 return ERROR_FAIL;
3154
3155 return xscale_init_arch_info(target, xscale, target->tap,
3156 target->variant);
3157 }
3158
3159 COMMAND_HANDLER(xscale_handle_debug_handler_command)
3160 {
3161 struct target *target = NULL;
3162 struct xscale_common *xscale;
3163 int retval;
3164 uint32_t handler_address;
3165
3166 if (CMD_ARGC < 2)
3167 {
3168 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3169 return ERROR_OK;
3170 }
3171
3172 if ((target = get_target(CMD_ARGV[0])) == NULL)
3173 {
3174 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3175 return ERROR_FAIL;
3176 }
3177
3178 xscale = target_to_xscale(target);
3179 retval = xscale_verify_pointer(CMD_CTX, xscale);
3180 if (retval != ERROR_OK)
3181 return retval;
3182
3183 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
3184
3185 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3186 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3187 {
3188 xscale->handler_address = handler_address;
3189 }
3190 else
3191 {
3192 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3193 return ERROR_FAIL;
3194 }
3195
3196 return ERROR_OK;
3197 }
3198
3199 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
3200 {
3201 struct target *target = NULL;
3202 struct xscale_common *xscale;
3203 int retval;
3204 uint32_t cache_clean_address;
3205
3206 if (CMD_ARGC < 2)
3207 {
3208 return ERROR_COMMAND_SYNTAX_ERROR;
3209 }
3210
3211 target = get_target(CMD_ARGV[0]);
3212 if (target == NULL)
3213 {
3214 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3215 return ERROR_FAIL;
3216 }
3217 xscale = target_to_xscale(target);
3218 retval = xscale_verify_pointer(CMD_CTX, xscale);
3219 if (retval != ERROR_OK)
3220 return retval;
3221
3222 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
3223
3224 if (cache_clean_address & 0xffff)
3225 {
3226 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3227 }
3228 else
3229 {
3230 xscale->cache_clean_address = cache_clean_address;
3231 }
3232
3233 return ERROR_OK;
3234 }
3235
3236 COMMAND_HANDLER(xscale_handle_cache_info_command)
3237 {
3238 struct target *target = get_current_target(CMD_CTX);
3239 struct xscale_common *xscale = target_to_xscale(target);
3240 int retval;
3241
3242 retval = xscale_verify_pointer(CMD_CTX, xscale);
3243 if (retval != ERROR_OK)
3244 return retval;
3245
3246 return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
3247 }
3248
3249 static int xscale_virt2phys(struct target *target,
3250 uint32_t virtual, uint32_t *physical)
3251 {
3252 struct xscale_common *xscale = target_to_xscale(target);
3253 uint32_t cb;
3254
3255 if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
3256 LOG_ERROR(xscale_not);
3257 return ERROR_TARGET_INVALID;
3258 }
3259
3260 uint32_t ret;
3261 int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
3262 virtual, &cb, &ret);
3263 if (retval != ERROR_OK)
3264 return retval;
3265 *physical = ret;
3266 return ERROR_OK;
3267 }
3268
3269 static int xscale_mmu(struct target *target, int *enabled)
3270 {
3271 struct xscale_common *xscale = target_to_xscale(target);
3272
3273 if (target->state != TARGET_HALTED)
3274 {
3275 LOG_ERROR("Target not halted");
3276 return ERROR_TARGET_INVALID;
3277 }
3278 *enabled = xscale->armv4_5_mmu.mmu_enabled;
3279 return ERROR_OK;
3280 }
3281
3282 COMMAND_HANDLER(xscale_handle_mmu_command)
3283 {
3284 struct target *target = get_current_target(CMD_CTX);
3285 struct xscale_common *xscale = target_to_xscale(target);
3286 int retval;
3287
3288 retval = xscale_verify_pointer(CMD_CTX, xscale);
3289 if (retval != ERROR_OK)
3290 return retval;
3291
3292 if (target->state != TARGET_HALTED)
3293 {
3294 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3295 return ERROR_OK;
3296 }
3297
3298 if (CMD_ARGC >= 1)
3299 {
3300 bool enable;
3301 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3302 if (enable)
3303 xscale_enable_mmu_caches(target, 1, 0, 0);
3304 else
3305 xscale_disable_mmu_caches(target, 1, 0, 0);
3306 xscale->armv4_5_mmu.mmu_enabled = enable;
3307 }
3308
3309 command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3310
3311 return ERROR_OK;
3312 }
3313
3314 COMMAND_HANDLER(xscale_handle_idcache_command)
3315 {
3316 struct target *target = get_current_target(CMD_CTX);
3317 struct xscale_common *xscale = target_to_xscale(target);
3318
3319 int retval = xscale_verify_pointer(CMD_CTX, xscale);
3320 if (retval != ERROR_OK)
3321 return retval;
3322
3323 if (target->state != TARGET_HALTED)
3324 {
3325 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3326 return ERROR_OK;
3327 }
3328
3329 bool icache = false;
3330 if (strcmp(CMD_NAME, "icache") == 0)
3331 icache = true;
3332 if (CMD_ARGC >= 1)
3333 {
3334 bool enable;
3335 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3336 if (icache) {
3337 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
3338 if (enable)
3339 xscale_enable_mmu_caches(target, 0, 0, 1);
3340 else
3341 xscale_disable_mmu_caches(target, 0, 0, 1);
3342 } else {
3343 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
3344 if (enable)
3345 xscale_enable_mmu_caches(target, 0, 1, 0);
3346 else
3347 xscale_disable_mmu_caches(target, 0, 1, 0);
3348 }
3349 }
3350
3351 bool enabled = icache ?
3352 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
3353 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
3354 const char *msg = enabled ? "enabled" : "disabled";
3355 command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
3356
3357 return ERROR_OK;
3358 }
3359
3360 COMMAND_HANDLER(xscale_handle_vector_catch_command)
3361 {
3362 struct target *target = get_current_target(CMD_CTX);
3363 struct xscale_common *xscale = target_to_xscale(target);
3364 int retval;
3365
3366 retval = xscale_verify_pointer(CMD_CTX, xscale);
3367 if (retval != ERROR_OK)
3368 return retval;
3369
3370 if (CMD_ARGC < 1)
3371 {
3372 command_print(CMD_CTX, "usage: xscale vector_catch [mask]");
3373 }
3374 else
3375 {
3376 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch);
3377 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3378 xscale_write_dcsr(target, -1, -1);
3379 }
3380
3381 command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3382
3383 return ERROR_OK;
3384 }
3385
3386
3387 COMMAND_HANDLER(xscale_handle_vector_table_command)
3388 {
3389 struct target *target = get_current_target(CMD_CTX);
3390 struct xscale_common *xscale = target_to_xscale(target);
3391 int err = 0;
3392 int retval;
3393
3394 retval = xscale_verify_pointer(CMD_CTX, xscale);
3395 if (retval != ERROR_OK)
3396 return retval;
3397
3398 if (CMD_ARGC == 0) /* print current settings */
3399 {
3400 int idx;
3401
3402 command_print(CMD_CTX, "active user-set static vectors:");
3403 for (idx = 1; idx < 8; idx++)
3404 if (xscale->static_low_vectors_set & (1 << idx))
3405 command_print(CMD_CTX, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
3406 for (idx = 1; idx < 8; idx++)
3407 if (xscale->static_high_vectors_set & (1 << idx))
3408 command_print(CMD_CTX, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
3409 return ERROR_OK;
3410 }
3411
3412 if (CMD_ARGC != 3)
3413 err = 1;
3414 else
3415 {
3416 int idx;
3417 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
3418 uint32_t vec;
3419 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
3420
3421 if (idx < 1 || idx >= 8)
3422 err = 1;
3423
3424 if (!err && strcmp(CMD_ARGV[0], "low") == 0)
3425 {
3426 xscale->static_low_vectors_set |= (1<<idx);
3427 xscale->static_low_vectors[idx] = vec;
3428 }
3429 else if (!err && (strcmp(CMD_ARGV[0], "high") == 0))
3430 {
3431 xscale->static_high_vectors_set |= (1<<idx);
3432 xscale->static_high_vectors[idx] = vec;
3433 }
3434 else
3435 err = 1;
3436 }
3437
3438 if (err)
3439 command_print(CMD_CTX, "usage: xscale vector_table <high|low> <index> <code>");
3440
3441 return ERROR_OK;
3442 }
3443
3444
3445 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
3446 {
3447 struct target *target = get_current_target(CMD_CTX);
3448 struct xscale_common *xscale = target_to_xscale(target);
3449 uint32_t dcsr_value;
3450 int retval;
3451
3452 retval = xscale_verify_pointer(CMD_CTX, xscale);
3453 if (retval != ERROR_OK)
3454 return retval;
3455
3456 if (target->state != TARGET_HALTED)
3457 {
3458 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3459 return ERROR_OK;
3460 }
3461
3462 if ((CMD_ARGC >= 1) && (strcmp("enable", CMD_ARGV[0]) == 0))
3463 {
3464 struct xscale_trace_data *td, *next_td;
3465 xscale->trace.buffer_enabled = 1;
3466
3467 /* free old trace data */
3468 td = xscale->trace.data;
3469 while (td)
3470 {
3471 next_td = td->next;
3472
3473 if (td->entries)
3474 free(td->entries);
3475 free(td);
3476 td = next_td;
3477 }
3478 xscale->trace.data = NULL;
3479 }
3480 else if ((CMD_ARGC >= 1) && (strcmp("disable", CMD_ARGV[0]) == 0))
3481 {
3482 xscale->trace.buffer_enabled = 0;
3483 }
3484
3485 if ((CMD_ARGC >= 2) && (strcmp("fill", CMD_ARGV[1]) == 0))
3486 {
3487 uint32_t fill = 1;
3488 if (CMD_ARGC >= 3)
3489 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], fill);
3490 xscale->trace.buffer_fill = fill;
3491 }
3492 else if ((CMD_ARGC >= 2) && (strcmp("wrap", CMD_ARGV[1]) == 0))
3493 {
3494 xscale->trace.buffer_fill = -1;
3495 }
3496
3497 command_print(CMD_CTX, "trace buffer %s (%s)",
3498 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3499 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3500
3501 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3502 if (xscale->trace.buffer_fill >= 0)
3503 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3504 else
3505 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3506
3507 return ERROR_OK;
3508 }
3509
3510 COMMAND_HANDLER(xscale_handle_trace_image_command)
3511 {
3512 struct target *target = get_current_target(CMD_CTX);
3513 struct xscale_common *xscale = target_to_xscale(target);
3514 int retval;
3515
3516 if (CMD_ARGC < 1)
3517 {
3518 command_print(CMD_CTX, "usage: xscale trace_image <file> [base address] [type]");
3519 return ERROR_OK;
3520 }
3521
3522 retval = xscale_verify_pointer(CMD_CTX, xscale);
3523 if (retval != ERROR_OK)
3524 return retval;
3525
3526 if (xscale->trace.image)
3527 {
3528 image_close(xscale->trace.image);
3529 free(xscale->trace.image);
3530 command_print(CMD_CTX, "previously loaded image found and closed");
3531 }
3532
3533 xscale->trace.image = malloc(sizeof(struct image));
3534 xscale->trace.image->base_address_set = 0;
3535 xscale->trace.image->start_address_set = 0;
3536
3537 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3538 if (CMD_ARGC >= 2)
3539 {
3540 xscale->trace.image->base_address_set = 1;
3541 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
3542 }
3543 else
3544 {
3545 xscale->trace.image->base_address_set = 0;
3546 }
3547
3548 if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
3549 {
3550 free(xscale->trace.image);
3551 xscale->trace.image = NULL;
3552 return ERROR_OK;
3553 }
3554
3555 return ERROR_OK;
3556 }
3557
3558 COMMAND_HANDLER(xscale_handle_dump_trace_command)
3559 {
3560 struct target *target = get_current_target(CMD_CTX);
3561 struct xscale_common *xscale = target_to_xscale(target);
3562 struct xscale_trace_data *trace_data;
3563 struct fileio file;
3564 int retval;
3565
3566 retval = xscale_verify_pointer(CMD_CTX, xscale);
3567 if (retval != ERROR_OK)
3568 return retval;
3569
3570 if (target->state != TARGET_HALTED)
3571 {
3572 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3573 return ERROR_OK;
3574 }
3575
3576 if (CMD_ARGC < 1)
3577 {
3578 command_print(CMD_CTX, "usage: xscale dump_trace <file>");
3579 return ERROR_OK;
3580 }
3581
3582 trace_data = xscale->trace.data;
3583
3584 if (!trace_data)
3585 {
3586 command_print(CMD_CTX, "no trace data collected");
3587 return ERROR_OK;
3588 }
3589
3590 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3591 {
3592 return ERROR_OK;
3593 }
3594
3595 while (trace_data)
3596 {
3597 int i;
3598
3599 fileio_write_u32(&file, trace_data->chkpt0);
3600 fileio_write_u32(&file, trace_data->chkpt1);
3601 fileio_write_u32(&file, trace_data->last_instruction);
3602 fileio_write_u32(&file, trace_data->depth);
3603
3604 for (i = 0; i < trace_data->depth; i++)
3605 fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3606
3607 trace_data = trace_data->next;
3608 }
3609
3610 fileio_close(&file);
3611
3612 return ERROR_OK;
3613 }
3614
3615 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
3616 {
3617 struct target *target = get_current_target(CMD_CTX);
3618 struct xscale_common *xscale = target_to_xscale(target);
3619 int retval;
3620
3621 retval = xscale_verify_pointer(CMD_CTX, xscale);
3622 if (retval != ERROR_OK)
3623 return retval;
3624
3625 xscale_analyze_trace(target, CMD_CTX);
3626
3627 return ERROR_OK;
3628 }
3629
3630 COMMAND_HANDLER(xscale_handle_cp15)
3631 {
3632 struct target *target = get_current_target(CMD_CTX);
3633 struct xscale_common *xscale = target_to_xscale(target);
3634 int retval;
3635
3636 retval = xscale_verify_pointer(CMD_CTX, xscale);
3637 if (retval != ERROR_OK)
3638 return retval;
3639
3640 if (target->state != TARGET_HALTED)
3641 {
3642 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3643 return ERROR_OK;
3644 }
3645 uint32_t reg_no = 0;
3646 struct reg *reg = NULL;
3647 if (CMD_ARGC > 0)
3648 {
3649 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
3650 /*translate from xscale cp15 register no to openocd register*/
3651 switch (reg_no)
3652 {
3653 case 0:
3654 reg_no = XSCALE_MAINID;
3655 break;
3656 case 1:
3657 reg_no = XSCALE_CTRL;
3658 break;
3659 case 2:
3660 reg_no = XSCALE_TTB;
3661 break;
3662 case 3:
3663 reg_no = XSCALE_DAC;
3664 break;
3665 case 5:
3666 reg_no = XSCALE_FSR;
3667 break;
3668 case 6:
3669 reg_no = XSCALE_FAR;
3670 break;
3671 case 13:
3672 reg_no = XSCALE_PID;
3673 break;
3674 case 15:
3675 reg_no = XSCALE_CPACCESS;
3676 break;
3677 default:
3678 command_print(CMD_CTX, "invalid register number");
3679 return ERROR_INVALID_ARGUMENTS;
3680 }
3681 reg = &xscale->reg_cache->reg_list[reg_no];
3682
3683 }
3684 if (CMD_ARGC == 1)
3685 {
3686 uint32_t value;
3687
3688 /* read cp15 control register */
3689 xscale_get_reg(reg);
3690 value = buf_get_u32(reg->value, 0, 32);
3691 command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
3692 }
3693 else if (CMD_ARGC == 2)
3694 {
3695 uint32_t value;
3696 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
3697
3698 /* send CP write request (command 0x41) */
3699 xscale_send_u32(target, 0x41);
3700
3701 /* send CP register number */
3702 xscale_send_u32(target, reg_no);
3703
3704 /* send CP register value */
3705 xscale_send_u32(target, value);
3706
3707 /* execute cpwait to ensure outstanding operations complete */
3708 xscale_send_u32(target, 0x53);
3709 }
3710 else
3711 {
3712 command_print(CMD_CTX, "usage: cp15 [register]<, [value]>");
3713 }
3714
3715 return ERROR_OK;
3716 }
3717
3718 static const struct command_registration xscale_exec_command_handlers[] = {
3719 {
3720 .name = "cache_info",
3721 .handler = xscale_handle_cache_info_command,
3722 .mode = COMMAND_EXEC,
3723 .help = "display information about CPU caches",
3724 },
3725 {
3726 .name = "mmu",
3727 .handler = xscale_handle_mmu_command,
3728 .mode = COMMAND_EXEC,
3729 .help = "enable or disable the MMU",
3730 .usage = "['enable'|'disable']",
3731 },
3732 {
3733 .name = "icache",
3734 .handler = xscale_handle_idcache_command,
3735 .mode = COMMAND_EXEC,
3736 .help = "display ICache state, optionally enabling or "
3737 "disabling it",
3738 .usage = "['enable'|'disable']",
3739 },
3740 {
3741 .name = "dcache",
3742 .handler = xscale_handle_idcache_command,
3743 .mode = COMMAND_EXEC,
3744 .help = "display DCache state, optionally enabling or "
3745 "disabling it",
3746 .usage = "['enable'|'disable']",
3747 },
3748 {
3749 .name = "vector_catch",
3750 .handler = xscale_handle_vector_catch_command,
3751 .mode = COMMAND_EXEC,
3752 .help = "set or display 8-bit mask of vectors "
3753 "that should trigger debug entry",
3754 .usage = "[mask]",
3755 },
3756 {
3757 .name = "vector_table",
3758 .handler = xscale_handle_vector_table_command,
3759 .mode = COMMAND_EXEC,
3760 .help = "set vector table entry in mini-ICache, "
3761 "or display current tables",
3762 .usage = "[('high'|'low') index code]",
3763 },
3764 {
3765 .name = "trace_buffer",
3766 .handler = xscale_handle_trace_buffer_command,
3767 .mode = COMMAND_EXEC,
3768 .help = "display trace buffer status, enable or disable "
3769 "tracing, and optionally reconfigure trace mode",
3770 .usage = "['enable'|'disable' ['fill' number|'wrap']]",
3771 },
3772 {
3773 .name = "dump_trace",
3774 .handler = xscale_handle_dump_trace_command,
3775 .mode = COMMAND_EXEC,
3776 .help = "dump content of trace buffer to file",
3777 .usage = "filename",
3778 },
3779 {
3780 .name = "analyze_trace",
3781 .handler = xscale_handle_analyze_trace_buffer_command,
3782 .mode = COMMAND_EXEC,
3783 .help = "analyze content of trace buffer",
3784 .usage = "",
3785 },
3786 {
3787 .name = "trace_image",
3788 .handler = xscale_handle_trace_image_command,
3789 .mode = COMMAND_EXEC,
3790 .help = "load image from file to address (default 0)",
3791 .usage = "filename [offset [filetype]]",
3792 },
3793 {
3794 .name = "cp15",
3795 .handler = xscale_handle_cp15,
3796 .mode = COMMAND_EXEC,
3797 .help = "Read or write coprocessor 15 register.",
3798 .usage = "register [value]",
3799 },
3800 COMMAND_REGISTRATION_DONE
3801 };
3802 static const struct command_registration xscale_any_command_handlers[] = {
3803 {
3804 .name = "debug_handler",
3805 .handler = xscale_handle_debug_handler_command,
3806 .mode = COMMAND_ANY,
3807 .help = "Change address used for debug handler.",
3808 .usage = "target address",
3809 },
3810 {
3811 .name = "cache_clean_address",
3812 .handler = xscale_handle_cache_clean_address_command,
3813 .mode = COMMAND_ANY,
3814 .help = "Change address used for cleaning data cache.",
3815 .usage = "address",
3816 },
3817 {
3818 .chain = xscale_exec_command_handlers,
3819 },
3820 COMMAND_REGISTRATION_DONE
3821 };
3822 static const struct command_registration xscale_command_handlers[] = {
3823 {
3824 .chain = arm_command_handlers,
3825 },
3826 {
3827 .name = "xscale",
3828 .mode = COMMAND_ANY,
3829 .help = "xscale command group",
3830 .chain = xscale_any_command_handlers,
3831 },
3832 COMMAND_REGISTRATION_DONE
3833 };
3834
3835 struct target_type xscale_target =
3836 {
3837 .name = "xscale",
3838
3839 .poll = xscale_poll,
3840 .arch_state = xscale_arch_state,
3841
3842 .target_request_data = NULL,
3843
3844 .halt = xscale_halt,
3845 .resume = xscale_resume,
3846 .step = xscale_step,
3847
3848 .assert_reset = xscale_assert_reset,
3849 .deassert_reset = xscale_deassert_reset,
3850 .soft_reset_halt = NULL,
3851
3852 /* REVISIT on some cores, allow exporting iwmmxt registers ... */
3853 .get_gdb_reg_list = arm_get_gdb_reg_list,
3854
3855 .read_memory = xscale_read_memory,
3856 .read_phys_memory = xscale_read_phys_memory,
3857 .write_memory = xscale_write_memory,
3858 .write_phys_memory = xscale_write_phys_memory,
3859 .bulk_write_memory = xscale_bulk_write_memory,
3860
3861 .checksum_memory = arm_checksum_memory,
3862 .blank_check_memory = arm_blank_check_memory,
3863
3864 .run_algorithm = armv4_5_run_algorithm,
3865
3866 .add_breakpoint = xscale_add_breakpoint,
3867 .remove_breakpoint = xscale_remove_breakpoint,
3868 .add_watchpoint = xscale_add_watchpoint,
3869 .remove_watchpoint = xscale_remove_watchpoint,
3870
3871 .commands = xscale_command_handlers,
3872 .target_create = xscale_target_create,
3873 .init_target = xscale_init_target,
3874
3875 .virt2phys = xscale_virt2phys,
3876 .mmu = xscale_mmu
3877 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)