1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "arm_simulator.h"
32 #include "arm_disassembler.h"
35 #include "binarybuffer.h"
36 #include "time_support.h"
37 #include "breakpoints.h"
43 #include <sys/types.h>
49 int xscale_register_commands(struct command_context_s
*cmd_ctx
);
51 /* forward declarations */
52 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
53 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
56 int xscale_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
57 enum target_state
xscale_poll(target_t
*target
);
58 int xscale_halt(target_t
*target
);
59 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
60 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
61 int xscale_debug_entry(target_t
*target
);
62 int xscale_restore_context(target_t
*target
);
64 int xscale_assert_reset(target_t
*target
);
65 int xscale_deassert_reset(target_t
*target
);
66 int xscale_soft_reset_halt(struct target_s
*target
);
67 int xscale_prepare_reset_halt(struct target_s
*target
);
69 int xscale_set_reg_u32(reg_t
*reg
, u32 value
);
71 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
72 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
);
74 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
75 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
76 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
);
77 int xscale_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
);
79 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
80 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
81 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
82 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
83 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
84 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
85 void xscale_enable_watchpoints(struct target_s
*target
);
86 void xscale_enable_breakpoints(struct target_s
*target
);
88 int xscale_read_trace(target_t
*target
);
90 target_type_t xscale_target
=
95 .arch_state
= xscale_arch_state
,
97 .target_request_data
= NULL
,
100 .resume
= xscale_resume
,
103 .assert_reset
= xscale_assert_reset
,
104 .deassert_reset
= xscale_deassert_reset
,
105 .soft_reset_halt
= xscale_soft_reset_halt
,
106 .prepare_reset_halt
= xscale_prepare_reset_halt
,
108 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
110 .read_memory
= xscale_read_memory
,
111 .write_memory
= xscale_write_memory
,
112 .bulk_write_memory
= xscale_bulk_write_memory
,
113 .checksum_memory
= xscale_checksum_memory
,
115 .run_algorithm
= armv4_5_run_algorithm
,
117 .add_breakpoint
= xscale_add_breakpoint
,
118 .remove_breakpoint
= xscale_remove_breakpoint
,
119 .add_watchpoint
= xscale_add_watchpoint
,
120 .remove_watchpoint
= xscale_remove_watchpoint
,
122 .register_commands
= xscale_register_commands
,
123 .target_command
= xscale_target_command
,
124 .init_target
= xscale_init_target
,
128 char* xscale_reg_list
[] =
130 "XSCALE_MAINID", /* 0 */
140 "XSCALE_IBCR0", /* 10 */
150 "XSCALE_RX", /* 20 */
154 xscale_reg_t xscale_reg_arch_info
[] =
156 {XSCALE_MAINID
, NULL
},
157 {XSCALE_CACHETYPE
, NULL
},
159 {XSCALE_AUXCTRL
, NULL
},
165 {XSCALE_CPACCESS
, NULL
},
166 {XSCALE_IBCR0
, NULL
},
167 {XSCALE_IBCR1
, NULL
},
170 {XSCALE_DBCON
, NULL
},
171 {XSCALE_TBREG
, NULL
},
172 {XSCALE_CHKPT0
, NULL
},
173 {XSCALE_CHKPT1
, NULL
},
174 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
175 {-1, NULL
}, /* TX accessed via JTAG */
176 {-1, NULL
}, /* RX accessed via JTAG */
177 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
180 int xscale_reg_arch_type
= -1;
182 int xscale_get_reg(reg_t
*reg
);
183 int xscale_set_reg(reg_t
*reg
, u8
*buf
);
185 int xscale_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
187 armv4_5_common_t
*armv4_5
= target
->arch_info
;
188 xscale_common_t
*xscale
= armv4_5
->arch_info
;
190 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
195 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
200 *armv4_5_p
= armv4_5
;
206 int xscale_jtag_set_instr(int chain_pos
, u32 new_instr
)
208 jtag_device_t
*device
= jtag_get_device(chain_pos
);
210 if (buf_get_u32(device
->cur_instr
, 0, device
->ir_length
) != new_instr
)
214 field
.device
= chain_pos
;
215 field
.num_bits
= device
->ir_length
;
216 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
217 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
218 field
.out_mask
= NULL
;
219 field
.in_value
= NULL
;
220 jtag_set_check_value(&field
, device
->expected
, device
->expected_mask
, NULL
);
222 jtag_add_ir_scan(1, &field
, -1, NULL
);
224 free(field
.out_value
);
230 int xscale_jtag_callback(enum jtag_event event
, void *priv
)
234 case JTAG_TRST_ASSERTED
:
236 case JTAG_TRST_RELEASED
:
238 case JTAG_SRST_ASSERTED
:
240 case JTAG_SRST_RELEASED
:
243 WARNING("unhandled JTAG event");
249 int xscale_read_dcsr(target_t
*target
)
251 armv4_5_common_t
*armv4_5
= target
->arch_info
;
252 xscale_common_t
*xscale
= armv4_5
->arch_info
;
256 scan_field_t fields
[3];
258 u8 field0_check_value
= 0x2;
259 u8 field0_check_mask
= 0x7;
261 u8 field2_check_value
= 0x0;
262 u8 field2_check_mask
= 0x1;
264 jtag_add_end_state(TAP_PD
);
265 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
267 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
268 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
270 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
271 fields
[0].num_bits
= 3;
272 fields
[0].out_value
= &field0
;
273 fields
[0].out_mask
= NULL
;
274 fields
[0].in_value
= NULL
;
275 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
277 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
278 fields
[1].num_bits
= 32;
279 fields
[1].out_value
= NULL
;
280 fields
[1].out_mask
= NULL
;
281 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
282 fields
[1].in_handler
= NULL
;
283 fields
[1].in_handler_priv
= NULL
;
284 fields
[1].in_check_value
= NULL
;
285 fields
[1].in_check_mask
= NULL
;
289 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
290 fields
[2].num_bits
= 1;
291 fields
[2].out_value
= &field2
;
292 fields
[2].out_mask
= NULL
;
293 fields
[2].in_value
= NULL
;
294 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
296 jtag_add_dr_scan(3, fields
, -1, NULL
);
298 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
300 ERROR("JTAG error while reading DCSR");
304 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
305 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
307 /* write the register with the value we just read
308 * on this second pass, only the first bit of field0 is guaranteed to be 0)
310 field0_check_mask
= 0x1;
311 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
312 fields
[1].in_value
= NULL
;
314 jtag_add_end_state(TAP_RTI
);
316 jtag_add_dr_scan(3, fields
, -1, NULL
);
321 int xscale_receive(target_t
*target
, u32
*buffer
, int num_words
)
323 armv4_5_common_t
*armv4_5
= target
->arch_info
;
324 xscale_common_t
*xscale
= armv4_5
->arch_info
;
326 enum tap_state path
[3];
327 scan_field_t fields
[3];
329 u8
*field0
= malloc(num_words
* 1);
330 u8 field0_check_value
= 0x2;
331 u8 field0_check_mask
= 0x6;
332 u32
*field1
= malloc(num_words
* 4);
333 u8 field2_check_value
= 0x0;
334 u8 field2_check_mask
= 0x1;
336 int words_scheduled
= 0;
345 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
346 fields
[0].num_bits
= 3;
347 fields
[0].out_value
= NULL
;
348 fields
[0].out_mask
= NULL
;
349 /* fields[0].in_value = field0; */
350 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
352 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
353 fields
[1].num_bits
= 32;
354 fields
[1].out_value
= NULL
;
355 fields
[1].out_mask
= NULL
;
356 fields
[1].in_value
= NULL
;
357 fields
[1].in_handler
= NULL
;
358 fields
[1].in_handler_priv
= NULL
;
359 fields
[1].in_check_value
= NULL
;
360 fields
[1].in_check_mask
= NULL
;
364 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
365 fields
[2].num_bits
= 1;
366 fields
[2].out_value
= NULL
;
367 fields
[2].out_mask
= NULL
;
368 fields
[2].in_value
= NULL
;
369 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
371 jtag_add_end_state(TAP_RTI
);
372 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
373 jtag_add_runtest(1, -1);
375 /* repeat until all words have been collected */
376 while (words_done
< num_words
)
380 for (i
= words_done
; i
< num_words
; i
++)
382 fields
[0].in_value
= &field0
[i
];
383 fields
[1].in_handler
= buf_to_u32_handler
;
384 fields
[1].in_handler_priv
= (u8
*)&field1
[i
];
386 jtag_add_pathmove(3, path
);
387 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
391 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
393 ERROR("JTAG error while receiving data from debug handler");
397 /* examine results */
398 for (i
= words_done
; i
< num_words
; i
++)
400 if (!(field0
[0] & 1))
402 /* move backwards if necessary */
404 for (j
= i
; j
< num_words
- 1; j
++)
406 field0
[j
] = field0
[j
+1];
407 field1
[j
] = field1
[j
+1];
412 words_done
+= words_scheduled
;
415 for (i
= 0; i
< num_words
; i
++)
416 *(buffer
++) = buf_get_u32((u8
*)&field1
[i
], 0, 32);
423 int xscale_read_tx(target_t
*target
, int consume
)
425 armv4_5_common_t
*armv4_5
= target
->arch_info
;
426 xscale_common_t
*xscale
= armv4_5
->arch_info
;
427 enum tap_state path
[3];
430 struct timeval timeout
, now
;
432 scan_field_t fields
[3];
434 u8 field0_check_value
= 0x2;
435 u8 field0_check_mask
= 0x6;
436 u8 field2_check_value
= 0x0;
437 u8 field2_check_mask
= 0x1;
439 jtag_add_end_state(TAP_RTI
);
441 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
447 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
448 fields
[0].num_bits
= 3;
449 fields
[0].out_value
= NULL
;
450 fields
[0].out_mask
= NULL
;
451 fields
[0].in_value
= &field0_in
;
452 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
454 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
455 fields
[1].num_bits
= 32;
456 fields
[1].out_value
= NULL
;
457 fields
[1].out_mask
= NULL
;
458 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
459 fields
[1].in_handler
= NULL
;
460 fields
[1].in_handler_priv
= NULL
;
461 fields
[1].in_check_value
= NULL
;
462 fields
[1].in_check_mask
= NULL
;
466 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
467 fields
[2].num_bits
= 1;
468 fields
[2].out_value
= NULL
;
469 fields
[2].out_mask
= NULL
;
470 fields
[2].in_value
= NULL
;
471 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
473 gettimeofday(&timeout
, NULL
);
474 timeval_add_time(&timeout
, 5, 0);
478 /* if we want to consume the register content (i.e. clear TX_READY),
479 * we have to go straight from Capture-DR to Shift-DR
480 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
483 jtag_add_pathmove(3, path
);
485 jtag_add_statemove(TAP_PD
);
487 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
489 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
491 ERROR("JTAG error while reading TX");
495 gettimeofday(&now
, NULL
);
496 if ((now
.tv_sec
> timeout
.tv_sec
) && (now
.tv_usec
> timeout
.tv_usec
))
498 ERROR("time out reading TX register");
499 return ERROR_TARGET_TIMEOUT
;
501 } while ((!(field0_in
& 1)) && consume
);
503 if (!(field0_in
& 1))
504 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
509 int xscale_write_rx(target_t
*target
)
511 armv4_5_common_t
*armv4_5
= target
->arch_info
;
512 xscale_common_t
*xscale
= armv4_5
->arch_info
;
515 struct timeval timeout
, now
;
517 scan_field_t fields
[3];
520 u8 field0_check_value
= 0x2;
521 u8 field0_check_mask
= 0x6;
523 u8 field2_check_value
= 0x0;
524 u8 field2_check_mask
= 0x1;
526 jtag_add_end_state(TAP_RTI
);
528 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
530 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
531 fields
[0].num_bits
= 3;
532 fields
[0].out_value
= &field0_out
;
533 fields
[0].out_mask
= NULL
;
534 fields
[0].in_value
= &field0_in
;
535 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
537 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
538 fields
[1].num_bits
= 32;
539 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
540 fields
[1].out_mask
= NULL
;
541 fields
[1].in_value
= NULL
;
542 fields
[1].in_handler
= NULL
;
543 fields
[1].in_handler_priv
= NULL
;
544 fields
[1].in_check_value
= NULL
;
545 fields
[1].in_check_mask
= NULL
;
549 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
550 fields
[2].num_bits
= 1;
551 fields
[2].out_value
= &field2
;
552 fields
[2].out_mask
= NULL
;
553 fields
[2].in_value
= NULL
;
554 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
556 gettimeofday(&timeout
, NULL
);
557 timeval_add_time(&timeout
, 5, 0);
559 /* poll until rx_read is low */
563 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
565 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
567 ERROR("JTAG error while writing RX");
571 gettimeofday(&now
, NULL
);
572 if ((now
.tv_sec
> timeout
.tv_sec
) && (now
.tv_usec
> timeout
.tv_usec
))
574 ERROR("time out writing RX register");
575 return ERROR_TARGET_TIMEOUT
;
577 } while (field0_in
& 1);
581 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
583 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
585 ERROR("JTAG error while writing RX");
592 /* send count elements of size byte to the debug handler */
593 int xscale_send(target_t
*target
, u8
*buffer
, int count
, int size
)
595 armv4_5_common_t
*armv4_5
= target
->arch_info
;
596 xscale_common_t
*xscale
= armv4_5
->arch_info
;
601 u8 output
[4] = {0, 0, 0, 0};
603 scan_field_t fields
[3];
606 u8 field0_check_value
= 0x2;
607 u8 field0_check_mask
= 0x6;
609 u8 field2_check_value
= 0x0;
610 u8 field2_check_mask
= 0x1;
612 jtag_add_end_state(TAP_RTI
);
614 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
616 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
617 fields
[0].num_bits
= 3;
618 fields
[0].out_value
= &field0_out
;
619 fields
[0].out_mask
= NULL
;
620 fields
[0].in_value
= &field0_in
;
621 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
623 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
624 fields
[1].num_bits
= 32;
625 fields
[1].out_value
= output
;
626 fields
[1].out_mask
= NULL
;
627 fields
[1].in_value
= NULL
;
628 fields
[1].in_handler
= NULL
;
629 fields
[1].in_handler_priv
= NULL
;
630 fields
[1].in_check_value
= NULL
;
631 fields
[1].in_check_mask
= NULL
;
635 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
636 fields
[2].num_bits
= 1;
637 fields
[2].out_value
= &field2
;
638 fields
[2].out_mask
= NULL
;
639 fields
[2].in_value
= NULL
;
640 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
642 while (done_count
++ < count
)
644 /* extract sized element from target-endian buffer, and put it
645 * into little-endian output buffer
650 buf_set_u32(output
, 0, 32, target_buffer_get_u32(target
, buffer
));
653 buf_set_u32(output
, 0, 32, target_buffer_get_u16(target
, buffer
));
659 ERROR("BUG: size neither 4, 2 nor 1");
663 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
667 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
669 ERROR("JTAG error while sending data to debug handler");
676 int xscale_send_u32(target_t
*target
, u32 value
)
678 armv4_5_common_t
*armv4_5
= target
->arch_info
;
679 xscale_common_t
*xscale
= armv4_5
->arch_info
;
681 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
682 return xscale_write_rx(target
);
685 int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
687 armv4_5_common_t
*armv4_5
= target
->arch_info
;
688 xscale_common_t
*xscale
= armv4_5
->arch_info
;
692 scan_field_t fields
[3];
694 u8 field0_check_value
= 0x2;
695 u8 field0_check_mask
= 0x7;
697 u8 field2_check_value
= 0x0;
698 u8 field2_check_mask
= 0x1;
701 xscale
->hold_rst
= hold_rst
;
703 if (ext_dbg_brk
!= -1)
704 xscale
->external_debug_break
= ext_dbg_brk
;
706 jtag_add_end_state(TAP_RTI
);
707 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
709 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
710 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
712 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
713 fields
[0].num_bits
= 3;
714 fields
[0].out_value
= &field0
;
715 fields
[0].out_mask
= NULL
;
716 fields
[0].in_value
= NULL
;
717 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
719 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
720 fields
[1].num_bits
= 32;
721 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
722 fields
[1].out_mask
= NULL
;
723 fields
[1].in_value
= NULL
;
724 fields
[1].in_handler
= NULL
;
725 fields
[1].in_handler_priv
= NULL
;
726 fields
[1].in_check_value
= NULL
;
727 fields
[1].in_check_mask
= NULL
;
731 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
732 fields
[2].num_bits
= 1;
733 fields
[2].out_value
= &field2
;
734 fields
[2].out_mask
= NULL
;
735 fields
[2].in_value
= NULL
;
736 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
738 jtag_add_dr_scan(3, fields
, -1, NULL
);
740 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
742 ERROR("JTAG error while writing DCSR");
746 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
747 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
752 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
753 unsigned int parity (unsigned int v
)
760 DEBUG("parity of 0x%x is %i", ov
, (0x6996 >> v
) & 1);
761 return (0x6996 >> v
) & 1;
764 int xscale_load_ic(target_t
*target
, int mini
, u32 va
, u32 buffer
[8])
766 armv4_5_common_t
*armv4_5
= target
->arch_info
;
767 xscale_common_t
*xscale
= armv4_5
->arch_info
;
772 scan_field_t fields
[2];
774 DEBUG("loading miniIC at 0x%8.8x", va
);
776 jtag_add_end_state(TAP_RTI
);
777 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
779 /* CMD is b010 for Main IC and b011 for Mini IC */
781 buf_set_u32(&cmd
, 0, 3, 0x3);
783 buf_set_u32(&cmd
, 0, 3, 0x2);
785 buf_set_u32(&cmd
, 3, 3, 0x0);
787 /* virtual address of desired cache line */
788 buf_set_u32(packet
, 0, 27, va
>> 5);
790 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
791 fields
[0].num_bits
= 6;
792 fields
[0].out_value
= &cmd
;
793 fields
[0].out_mask
= NULL
;
794 fields
[0].in_value
= NULL
;
795 fields
[0].in_check_value
= NULL
;
796 fields
[0].in_check_mask
= NULL
;
797 fields
[0].in_handler
= NULL
;
798 fields
[0].in_handler_priv
= NULL
;
800 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
801 fields
[1].num_bits
= 27;
802 fields
[1].out_value
= packet
;
803 fields
[1].out_mask
= NULL
;
804 fields
[1].in_value
= NULL
;
805 fields
[1].in_check_value
= NULL
;
806 fields
[1].in_check_mask
= NULL
;
807 fields
[1].in_handler
= NULL
;
808 fields
[1].in_handler_priv
= NULL
;
810 jtag_add_dr_scan(2, fields
, -1, NULL
);
812 fields
[0].num_bits
= 32;
813 fields
[0].out_value
= packet
;
815 fields
[1].num_bits
= 1;
816 fields
[1].out_value
= &cmd
;
818 for (word
= 0; word
< 8; word
++)
820 buf_set_u32(packet
, 0, 32, buffer
[word
]);
821 cmd
= parity(*((u32
*)packet
));
822 jtag_add_dr_scan(2, fields
, -1, NULL
);
825 jtag_execute_queue();
830 int xscale_invalidate_ic_line(target_t
*target
, u32 va
)
832 armv4_5_common_t
*armv4_5
= target
->arch_info
;
833 xscale_common_t
*xscale
= armv4_5
->arch_info
;
837 scan_field_t fields
[2];
839 jtag_add_end_state(TAP_RTI
);
840 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
842 /* CMD for invalidate IC line b000, bits [6:4] b000 */
843 buf_set_u32(&cmd
, 0, 6, 0x0);
845 /* virtual address of desired cache line */
846 buf_set_u32(packet
, 0, 27, va
>> 5);
848 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
849 fields
[0].num_bits
= 6;
850 fields
[0].out_value
= &cmd
;
851 fields
[0].out_mask
= NULL
;
852 fields
[0].in_value
= NULL
;
853 fields
[0].in_check_value
= NULL
;
854 fields
[0].in_check_mask
= NULL
;
855 fields
[0].in_handler
= NULL
;
856 fields
[0].in_handler_priv
= NULL
;
858 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
859 fields
[1].num_bits
= 27;
860 fields
[1].out_value
= packet
;
861 fields
[1].out_mask
= NULL
;
862 fields
[1].in_value
= NULL
;
863 fields
[1].in_check_value
= NULL
;
864 fields
[1].in_check_mask
= NULL
;
865 fields
[1].in_handler
= NULL
;
866 fields
[1].in_handler_priv
= NULL
;
868 jtag_add_dr_scan(2, fields
, -1, NULL
);
873 int xscale_update_vectors(target_t
*target
)
875 armv4_5_common_t
*armv4_5
= target
->arch_info
;
876 xscale_common_t
*xscale
= armv4_5
->arch_info
;
879 u32 low_reset_branch
, high_reset_branch
;
881 for (i
= 1; i
< 8; i
++)
883 /* if there's a static vector specified for this exception, override */
884 if (xscale
->static_high_vectors_set
& (1 << i
))
886 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
890 if (target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]) != ERROR_OK
)
892 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
897 for (i
= 1; i
< 8; i
++)
899 if (xscale
->static_low_vectors_set
& (1 << i
))
901 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
905 if (target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]) != ERROR_OK
)
907 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
912 /* calculate branches to debug handler */
913 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
914 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
916 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
917 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
919 /* invalidate and load exception vectors in mini i-cache */
920 xscale_invalidate_ic_line(target
, 0x0);
921 xscale_invalidate_ic_line(target
, 0xffff0000);
923 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
924 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
929 int xscale_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
931 armv4_5_common_t
*armv4_5
= target
->arch_info
;
932 xscale_common_t
*xscale
= armv4_5
->arch_info
;
936 "disabled", "enabled"
939 char *arch_dbg_reason
[] =
941 "", "\n(processor reset)", "\n(trace buffer full)"
944 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
946 ERROR("BUG: called for a non-ARMv4/5 target");
950 snprintf(buf
, buf_size
,
951 "target halted in %s state due to %s, current mode: %s\n"
952 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
953 "MMU: %s, D-Cache: %s, I-Cache: %s"
955 armv4_5_state_strings
[armv4_5
->core_state
],
956 target_debug_reason_strings
[target
->debug_reason
],
957 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
958 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
959 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
960 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
961 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
962 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
963 arch_dbg_reason
[xscale
->arch_debug_reason
]);
968 enum target_state
xscale_poll(target_t
*target
)
971 armv4_5_common_t
*armv4_5
= target
->arch_info
;
972 xscale_common_t
*xscale
= armv4_5
->arch_info
;
974 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
976 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
978 enum target_state previous_state
= target
->state
;
980 /* there's data to read from the tx register, we entered debug state */
981 xscale
->handler_running
= 1;
983 target
->state
= TARGET_HALTED
;
985 /* process debug entry, fetching current mode regs */
986 if ((retval
= xscale_debug_entry(target
)) != ERROR_OK
)
989 /* debug_entry could have overwritten target state (i.e. immediate resume)
990 * don't signal event handlers in that case
992 if (target
->state
!= TARGET_HALTED
)
993 return target
->state
;
995 /* if target was running, signal that we halted
996 * otherwise we reentered from debug execution */
997 if (previous_state
== TARGET_RUNNING
)
998 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1000 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1002 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1004 ERROR("error while polling TX register");
1009 return target
->state
;
1012 int xscale_debug_entry(target_t
*target
)
1014 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1015 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1017 u32
*buffer
= malloc(4 * 10);
1022 /* clear external dbg break (will be written on next DCSR read) */
1023 xscale
->external_debug_break
= 0;
1024 xscale_read_dcsr(target
);
1026 /* get r0, pc, r1 to r7 and cpsr */
1027 xscale_receive(target
, buffer
, 10);
1029 /* move r0 from buffer to register cache */
1030 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
1031 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1032 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1033 DEBUG("r0: 0x%8.8x", buffer
[0]);
1035 /* move pc from buffer to register cache */
1036 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
1037 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1038 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1039 DEBUG("pc: 0x%8.8x", buffer
[1]);
1041 /* move data from buffer to register cache */
1042 for (i
= 1; i
<= 7; i
++)
1044 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
1045 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
1046 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
1047 DEBUG("r%i: 0x%8.8x", i
, buffer
[i
+ 1]);
1050 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
1051 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1052 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1053 DEBUG("cpsr: 0x%8.8x", buffer
[9]);
1055 armv4_5
->core_mode
= buffer
[9] & 0x1f;
1056 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1058 target
->state
= TARGET_UNKNOWN
;
1059 ERROR("cpsr contains invalid mode value - communication failure");
1060 return ERROR_TARGET_FAILURE
;
1062 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1064 if (buffer
[9] & 0x20)
1065 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1067 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1069 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1070 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1072 xscale_receive(target
, buffer
, 8);
1073 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1074 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1075 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1079 /* r8 to r14, but no spsr */
1080 xscale_receive(target
, buffer
, 7);
1083 /* move data from buffer to register cache */
1084 for (i
= 8; i
<= 14; i
++)
1086 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1087 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1088 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1091 /* examine debug reason */
1092 xscale_read_dcsr(target
);
1093 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1095 /* stored PC (for calculating fixup) */
1096 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1100 case 0x0: /* Processor reset */
1101 target
->debug_reason
= DBG_REASON_DBGRQ
;
1102 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1105 case 0x1: /* Instruction breakpoint hit */
1106 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1107 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1110 case 0x2: /* Data breakpoint hit */
1111 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1112 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1115 case 0x3: /* BKPT instruction executed */
1116 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1117 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1120 case 0x4: /* Ext. debug event */
1121 target
->debug_reason
= DBG_REASON_DBGRQ
;
1122 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1125 case 0x5: /* Vector trap occured */
1126 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1127 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1130 case 0x6: /* Trace buffer full break */
1131 target
->debug_reason
= DBG_REASON_DBGRQ
;
1132 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1135 case 0x7: /* Reserved */
1137 ERROR("Method of Entry is 'Reserved'");
1142 /* apply PC fixup */
1143 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1145 /* on the first debug entry, identify cache type */
1146 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1150 /* read cp15 cache type register */
1151 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1152 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1154 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1157 /* examine MMU and Cache settings */
1158 /* read cp15 control register */
1159 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1160 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1161 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1162 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1163 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1165 /* tracing enabled, read collected trace data */
1166 if (xscale
->trace
.buffer_enabled
)
1168 xscale_read_trace(target
);
1169 xscale
->trace
.buffer_fill
--;
1171 /* resume if we're still collecting trace data */
1172 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1173 && (xscale
->trace
.buffer_fill
> 0))
1175 xscale_resume(target
, 1, 0x0, 1, 0);
1179 xscale
->trace
.buffer_enabled
= 0;
1186 int xscale_halt(target_t
*target
)
1188 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1189 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1191 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1193 if (target
->state
== TARGET_HALTED
)
1195 WARNING("target was already halted");
1196 return ERROR_TARGET_ALREADY_HALTED
;
1198 else if (target
->state
== TARGET_UNKNOWN
)
1200 /* this must not happen for a xscale target */
1201 ERROR("target was in unknown state when halt was requested");
1204 else if (target
->state
== TARGET_RESET
)
1206 DEBUG("target->state == TARGET_RESET");
1210 /* assert external dbg break */
1211 xscale
->external_debug_break
= 1;
1212 xscale_read_dcsr(target
);
1214 target
->debug_reason
= DBG_REASON_DBGRQ
;
1220 int xscale_enable_single_step(struct target_s
*target
, u32 next_pc
)
1222 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1223 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1224 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1226 if (xscale
->ibcr0_used
)
1228 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1232 xscale_unset_breakpoint(target
, ibcr0_bp
);
1236 ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1241 xscale_set_reg_u32(ibcr0
, next_pc
| 0x1);
1246 int xscale_disable_single_step(struct target_s
*target
)
1248 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1249 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1250 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1252 xscale_set_reg_u32(ibcr0
, 0x0);
1257 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1259 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1260 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1261 breakpoint_t
*breakpoint
= target
->breakpoints
;
1270 if (target
->state
!= TARGET_HALTED
)
1272 WARNING("target not halted");
1273 return ERROR_TARGET_NOT_HALTED
;
1276 if (!debug_execution
)
1278 target_free_all_working_areas(target
);
1281 /* update vector tables */
1282 xscale_update_vectors(target
);
1284 /* current = 1: continue on current pc, otherwise continue at <address> */
1286 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1288 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1290 /* if we're at the reset vector, we have to simulate the branch */
1291 if (current_pc
== 0x0)
1293 arm_simulate_step(target
, NULL
);
1294 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1297 /* the front-end may request us not to handle breakpoints */
1298 if (handle_breakpoints
)
1300 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1304 /* there's a breakpoint at the current PC, we have to step over it */
1305 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1306 xscale_unset_breakpoint(target
, breakpoint
);
1308 /* calculate PC of next instruction */
1309 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1312 target_read_u32(target
, current_pc
, ¤t_opcode
);
1313 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1316 DEBUG("enable single-step");
1317 xscale_enable_single_step(target
, next_pc
);
1319 /* restore banked registers */
1320 xscale_restore_context(target
);
1322 /* send resume request (command 0x30 or 0x31)
1323 * clean the trace buffer if it is to be enabled (0x62) */
1324 if (xscale
->trace
.buffer_enabled
)
1326 xscale_send_u32(target
, 0x62);
1327 xscale_send_u32(target
, 0x31);
1330 xscale_send_u32(target
, 0x30);
1333 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1334 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1336 for (i
= 7; i
>= 0; i
--)
1339 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1340 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1344 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1345 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1347 /* wait for and process debug entry */
1348 xscale_debug_entry(target
);
1350 DEBUG("disable single-step");
1351 xscale_disable_single_step(target
);
1353 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1354 xscale_set_breakpoint(target
, breakpoint
);
1358 /* enable any pending breakpoints and watchpoints */
1359 xscale_enable_breakpoints(target
);
1360 xscale_enable_watchpoints(target
);
1362 /* restore banked registers */
1363 xscale_restore_context(target
);
1365 /* send resume request (command 0x30 or 0x31)
1366 * clean the trace buffer if it is to be enabled (0x62) */
1367 if (xscale
->trace
.buffer_enabled
)
1369 xscale_send_u32(target
, 0x62);
1370 xscale_send_u32(target
, 0x31);
1373 xscale_send_u32(target
, 0x30);
1376 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1377 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1379 for (i
= 7; i
>= 0; i
--)
1382 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1383 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1387 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1388 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1390 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1392 if (!debug_execution
)
1394 /* registers are now invalid */
1395 armv4_5_invalidate_core_regs(target
);
1396 target
->state
= TARGET_RUNNING
;
1397 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1401 target
->state
= TARGET_DEBUG_RUNNING
;
1402 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1405 DEBUG("target resumed");
1407 xscale
->handler_running
= 1;
1412 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1414 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1415 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1416 breakpoint_t
*breakpoint
= target
->breakpoints
;
1418 u32 current_pc
, next_pc
;
1422 if (target
->state
!= TARGET_HALTED
)
1424 WARNING("target not halted");
1425 return ERROR_TARGET_NOT_HALTED
;
1428 /* current = 1: continue on current pc, otherwise continue at <address> */
1430 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1432 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1434 /* if we're at the reset vector, we have to simulate the step */
1435 if (current_pc
== 0x0)
1437 arm_simulate_step(target
, NULL
);
1438 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1440 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1441 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1446 /* the front-end may request us not to handle breakpoints */
1447 if (handle_breakpoints
)
1448 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1450 xscale_unset_breakpoint(target
, breakpoint
);
1453 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1455 /* calculate PC of next instruction */
1456 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1459 target_read_u32(target
, current_pc
, ¤t_opcode
);
1460 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1463 DEBUG("enable single-step");
1464 xscale_enable_single_step(target
, next_pc
);
1466 /* restore banked registers */
1467 xscale_restore_context(target
);
1469 /* send resume request (command 0x30 or 0x31)
1470 * clean the trace buffer if it is to be enabled (0x62) */
1471 if (xscale
->trace
.buffer_enabled
)
1473 xscale_send_u32(target
, 0x62);
1474 xscale_send_u32(target
, 0x31);
1477 xscale_send_u32(target
, 0x30);
1480 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1481 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1483 for (i
= 7; i
>= 0; i
--)
1486 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1487 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1491 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1492 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1494 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1496 /* registers are now invalid */
1497 armv4_5_invalidate_core_regs(target
);
1499 /* wait for and process debug entry */
1500 xscale_debug_entry(target
);
1502 DEBUG("disable single-step");
1503 xscale_disable_single_step(target
);
1505 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1509 xscale_set_breakpoint(target
, breakpoint
);
1512 DEBUG("target stepped");
1518 int xscale_assert_reset(target_t
*target
)
1520 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1521 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1523 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1525 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1526 * end up in T-L-R, which would reset JTAG
1528 jtag_add_end_state(TAP_RTI
);
1529 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
1531 /* set Hold reset, Halt mode and Trap Reset */
1532 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1533 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1534 xscale_write_dcsr(target
, 1, 0);
1536 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1537 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, 0x7f);
1538 jtag_execute_queue();
1541 jtag_add_reset(0, 1);
1543 /* sleep 1ms, to be sure we fulfill any requirements */
1544 jtag_add_sleep(1000);
1545 jtag_execute_queue();
1547 target
->state
= TARGET_RESET
;
1552 int xscale_deassert_reset(target_t
*target
)
1554 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1555 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1557 fileio_t debug_handler
;
1565 breakpoint_t
*breakpoint
= target
->breakpoints
;
1569 xscale
->ibcr_available
= 2;
1570 xscale
->ibcr0_used
= 0;
1571 xscale
->ibcr1_used
= 0;
1573 xscale
->dbr_available
= 2;
1574 xscale
->dbr0_used
= 0;
1575 xscale
->dbr1_used
= 0;
1577 /* mark all hardware breakpoints as unset */
1580 if (breakpoint
->type
== BKPT_HARD
)
1582 breakpoint
->set
= 0;
1584 breakpoint
= breakpoint
->next
;
1587 if (!xscale
->handler_installed
)
1590 jtag_add_reset(0, 0);
1592 /* wait 300ms; 150 and 100ms were not enough */
1593 jtag_add_sleep(3000000);
1595 jtag_add_runtest(2030, TAP_RTI
);
1596 jtag_execute_queue();
1598 /* set Hold reset, Halt mode and Trap Reset */
1599 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1600 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1601 xscale_write_dcsr(target
, 1, 0);
1603 /* Load debug handler */
1604 if (fileio_open(&debug_handler
, PKGLIBDIR
"/xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1606 ERROR("file open error: %s", debug_handler
.error_str
);
1610 if ((binary_size
= debug_handler
.size
) % 4)
1612 ERROR("debug_handler.bin: size not a multiple of 4");
1616 if (binary_size
> 0x800)
1618 ERROR("debug_handler.bin: larger than 2kb");
1622 binary_size
= CEIL(binary_size
, 32) * 32;
1624 address
= xscale
->handler_address
;
1625 while (binary_size
> 0)
1630 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1632 ERROR("reading debug handler failed: %s", debug_handler
.error_str
);
1635 for (i
= 0; i
< buf_cnt
; i
+= 4)
1637 /* convert LE buffer to host-endian u32 */
1638 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1641 for (; buf_cnt
< 32; buf_cnt
+= 4)
1643 cache_line
[buf_cnt
/ 4] = 0xe1a08008;
1646 /* only load addresses other than the reset vectors */
1647 if ((address
% 0x400) != 0x0)
1649 xscale_load_ic(target
, 1, address
, cache_line
);
1653 binary_size
-= buf_cnt
;
1656 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
1657 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
1659 jtag_add_runtest(30, TAP_RTI
);
1661 jtag_add_sleep(100000);
1663 /* set Hold reset, Halt mode and Trap Reset */
1664 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1665 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1666 xscale_write_dcsr(target
, 1, 0);
1668 /* clear Hold reset to let the target run (should enter debug handler) */
1669 xscale_write_dcsr(target
, 0, 1);
1670 target
->state
= TARGET_RUNNING
;
1672 if ((target
->reset_mode
!= RESET_HALT
) && (target
->reset_mode
!= RESET_INIT
))
1674 jtag_add_sleep(10000);
1676 /* we should have entered debug now */
1677 xscale_debug_entry(target
);
1678 target
->state
= TARGET_HALTED
;
1680 /* resume the target */
1681 xscale_resume(target
, 1, 0x0, 1, 0);
1686 jtag_add_reset(0, 0);
1693 int xscale_soft_reset_halt(struct target_s
*target
)
1699 int xscale_prepare_reset_halt(struct target_s
*target
)
1701 /* nothing to be done for reset_halt on XScale targets
1702 * we always halt after a reset to upload the debug handler
1707 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1713 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1719 int xscale_full_context(target_t
*target
)
1721 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1729 if (target
->state
!= TARGET_HALTED
)
1731 WARNING("target not halted");
1732 return ERROR_TARGET_NOT_HALTED
;
1735 buffer
= malloc(4 * 8);
1737 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1738 * we can't enter User mode on an XScale (unpredictable),
1739 * but User shares registers with SYS
1741 for(i
= 1; i
< 7; i
++)
1745 /* check if there are invalid registers in the current mode
1747 for (j
= 0; j
<= 16; j
++)
1749 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1757 /* request banked registers */
1758 xscale_send_u32(target
, 0x0);
1761 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1762 tmp_cpsr
|= 0xc0; /* I/F bits */
1764 /* send CPSR for desired mode */
1765 xscale_send_u32(target
, tmp_cpsr
);
1767 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1768 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1770 xscale_receive(target
, buffer
, 8);
1771 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1772 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1773 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1777 xscale_receive(target
, buffer
, 7);
1780 /* move data from buffer to register cache */
1781 for (j
= 8; j
<= 14; j
++)
1783 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1784 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1785 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1795 int xscale_restore_context(target_t
*target
)
1797 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1803 if (target
->state
!= TARGET_HALTED
)
1805 WARNING("target not halted");
1806 return ERROR_TARGET_NOT_HALTED
;
1809 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1810 * we can't enter User mode on an XScale (unpredictable),
1811 * but User shares registers with SYS
1813 for(i
= 1; i
< 7; i
++)
1817 /* check if there are invalid registers in the current mode
1819 for (j
= 8; j
<= 14; j
++)
1821 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1825 /* if not USR/SYS, check if the SPSR needs to be written */
1826 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1828 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1836 /* send banked registers */
1837 xscale_send_u32(target
, 0x1);
1840 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1841 tmp_cpsr
|= 0xc0; /* I/F bits */
1843 /* send CPSR for desired mode */
1844 xscale_send_u32(target
, tmp_cpsr
);
1846 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1847 for (j
= 8; j
<= 14; j
++)
1849 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1850 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1853 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1855 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1856 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1864 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1866 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1867 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1871 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1873 if (target
->state
!= TARGET_HALTED
)
1875 WARNING("target not halted");
1876 return ERROR_TARGET_NOT_HALTED
;
1879 /* sanitize arguments */
1880 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1881 return ERROR_INVALID_ARGUMENTS
;
1883 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1884 return ERROR_TARGET_UNALIGNED_ACCESS
;
1886 /* send memory read request (command 0x1n, n: access size) */
1887 xscale_send_u32(target
, 0x10 | size
);
1889 /* send base address for read request */
1890 xscale_send_u32(target
, address
);
1892 /* send number of requested data words */
1893 xscale_send_u32(target
, count
);
1895 /* receive data from target (count times 32-bit words in host endianness) */
1896 buf32
= malloc(4 * count
);
1897 xscale_receive(target
, buf32
, count
);
1899 /* extract data from host-endian buffer into byte stream */
1900 for (i
= 0; i
< count
; i
++)
1905 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1909 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1913 *buffer
++ = buf32
[i
] & 0xff;
1916 ERROR("should never get here");
1923 /* examine DCSR, to see if Sticky Abort (SA) got set */
1924 xscale_read_dcsr(target
);
1925 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1928 xscale_send_u32(target
, 0x60);
1930 return ERROR_TARGET_DATA_ABORT
;
1936 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1938 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1939 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1941 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1943 if (target
->state
!= TARGET_HALTED
)
1945 WARNING("target not halted");
1946 return ERROR_TARGET_NOT_HALTED
;
1949 /* sanitize arguments */
1950 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1951 return ERROR_INVALID_ARGUMENTS
;
1953 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1954 return ERROR_TARGET_UNALIGNED_ACCESS
;
1956 /* send memory write request (command 0x2n, n: access size) */
1957 xscale_send_u32(target
, 0x20 | size
);
1959 /* send base address for read request */
1960 xscale_send_u32(target
, address
);
1962 /* send number of requested data words to be written*/
1963 xscale_send_u32(target
, count
);
1965 /* extract data from host-endian buffer into byte stream */
1967 for (i
= 0; i
< count
; i
++)
1972 value
= target_buffer_get_u32(target
, buffer
);
1973 xscale_send_u32(target
, value
);
1977 value
= target_buffer_get_u16(target
, buffer
);
1978 xscale_send_u32(target
, value
);
1983 xscale_send_u32(target
, value
);
1987 ERROR("should never get here");
1992 xscale_send(target
, buffer
, count
, size
);
1994 /* examine DCSR, to see if Sticky Abort (SA) got set */
1995 xscale_read_dcsr(target
);
1996 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1999 xscale_send_u32(target
, 0x60);
2001 return ERROR_TARGET_DATA_ABORT
;
2007 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2009 xscale_write_memory(target
, address
, 4, count
, buffer
);
2014 int xscale_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
2016 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2019 u32
xscale_get_ttb(target_t
*target
)
2021 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2022 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2025 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2026 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2031 void xscale_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2033 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2034 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2037 /* read cp15 control register */
2038 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2039 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2042 cp15_control
&= ~0x1U
;
2047 xscale_send_u32(target
, 0x50);
2048 xscale_send_u32(target
, xscale
->cache_clean_address
);
2050 /* invalidate DCache */
2051 xscale_send_u32(target
, 0x51);
2053 cp15_control
&= ~0x4U
;
2058 /* invalidate ICache */
2059 xscale_send_u32(target
, 0x52);
2060 cp15_control
&= ~0x1000U
;
2063 /* write new cp15 control register */
2064 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2066 /* execute cpwait to ensure outstanding operations complete */
2067 xscale_send_u32(target
, 0x53);
2070 void xscale_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2072 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2073 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2076 /* read cp15 control register */
2077 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2078 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2081 cp15_control
|= 0x1U
;
2084 cp15_control
|= 0x4U
;
2087 cp15_control
|= 0x1000U
;
2089 /* write new cp15 control register */
2090 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2092 /* execute cpwait to ensure outstanding operations complete */
2093 xscale_send_u32(target
, 0x53);
2096 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2098 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2099 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2101 if (target
->state
!= TARGET_HALTED
)
2103 WARNING("target not halted");
2104 return ERROR_TARGET_NOT_HALTED
;
2107 if (xscale
->force_hw_bkpts
)
2108 breakpoint
->type
= BKPT_HARD
;
2110 if (breakpoint
->set
)
2112 WARNING("breakpoint already set");
2116 if (breakpoint
->type
== BKPT_HARD
)
2118 u32 value
= breakpoint
->address
| 1;
2119 if (!xscale
->ibcr0_used
)
2121 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2122 xscale
->ibcr0_used
= 1;
2123 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2125 else if (!xscale
->ibcr1_used
)
2127 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2128 xscale
->ibcr1_used
= 1;
2129 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2133 ERROR("BUG: no hardware comparator available");
2137 else if (breakpoint
->type
== BKPT_SOFT
)
2139 if (breakpoint
->length
== 4)
2141 /* keep the original instruction in target endianness */
2142 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2143 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2144 target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
);
2148 /* keep the original instruction in target endianness */
2149 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2150 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2151 target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
);
2153 breakpoint
->set
= 1;
2160 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2162 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2163 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2165 if (target
->state
!= TARGET_HALTED
)
2167 WARNING("target not halted");
2168 return ERROR_TARGET_NOT_HALTED
;
2171 if (xscale
->force_hw_bkpts
)
2173 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
2174 breakpoint
->type
= BKPT_HARD
;
2177 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2179 INFO("no breakpoint unit available for hardware breakpoint");
2180 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2184 xscale
->ibcr_available
--;
2187 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2189 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2190 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2196 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2198 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2199 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2201 if (target
->state
!= TARGET_HALTED
)
2203 WARNING("target not halted");
2204 return ERROR_TARGET_NOT_HALTED
;
2207 if (!breakpoint
->set
)
2209 WARNING("breakpoint not set");
2213 if (breakpoint
->type
== BKPT_HARD
)
2215 if (breakpoint
->set
== 1)
2217 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2218 xscale
->ibcr0_used
= 0;
2220 else if (breakpoint
->set
== 2)
2222 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2223 xscale
->ibcr1_used
= 0;
2225 breakpoint
->set
= 0;
2229 /* restore original instruction (kept in target endianness) */
2230 if (breakpoint
->length
== 4)
2232 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2236 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2238 breakpoint
->set
= 0;
2244 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2246 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2247 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2249 if (target
->state
!= TARGET_HALTED
)
2251 WARNING("target not halted");
2252 return ERROR_TARGET_NOT_HALTED
;
2255 if (breakpoint
->set
)
2257 xscale_unset_breakpoint(target
, breakpoint
);
2260 if (breakpoint
->type
== BKPT_HARD
)
2261 xscale
->ibcr_available
++;
2266 int xscale_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2268 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2269 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2271 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2272 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2274 if (target
->state
!= TARGET_HALTED
)
2276 WARNING("target not halted");
2277 return ERROR_TARGET_NOT_HALTED
;
2280 xscale_get_reg(dbcon
);
2282 switch (watchpoint
->rw
)
2294 ERROR("BUG: watchpoint->rw neither read, write nor access");
2297 if (!xscale
->dbr0_used
)
2299 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2300 dbcon_value
|= enable
;
2301 xscale_set_reg_u32(dbcon
, dbcon_value
);
2302 watchpoint
->set
= 1;
2303 xscale
->dbr0_used
= 1;
2305 else if (!xscale
->dbr1_used
)
2307 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2308 dbcon_value
|= enable
<< 2;
2309 xscale_set_reg_u32(dbcon
, dbcon_value
);
2310 watchpoint
->set
= 2;
2311 xscale
->dbr1_used
= 1;
2315 ERROR("BUG: no hardware comparator available");
2322 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2324 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2325 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2327 if (target
->state
!= TARGET_HALTED
)
2329 WARNING("target not halted");
2330 return ERROR_TARGET_NOT_HALTED
;
2333 if (xscale
->dbr_available
< 1)
2335 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2338 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2340 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2343 xscale
->dbr_available
--;
2348 int xscale_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2350 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2351 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2352 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2353 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2355 if (target
->state
!= TARGET_HALTED
)
2357 WARNING("target not halted");
2358 return ERROR_TARGET_NOT_HALTED
;
2361 if (!watchpoint
->set
)
2363 WARNING("breakpoint not set");
2367 if (watchpoint
->set
== 1)
2369 dbcon_value
&= ~0x3;
2370 xscale_set_reg_u32(dbcon
, dbcon_value
);
2371 xscale
->dbr0_used
= 0;
2373 else if (watchpoint
->set
== 2)
2375 dbcon_value
&= ~0xc;
2376 xscale_set_reg_u32(dbcon
, dbcon_value
);
2377 xscale
->dbr1_used
= 0;
2379 watchpoint
->set
= 0;
2384 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2386 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2387 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2389 if (target
->state
!= TARGET_HALTED
)
2391 WARNING("target not halted");
2392 return ERROR_TARGET_NOT_HALTED
;
2395 if (watchpoint
->set
)
2397 xscale_unset_watchpoint(target
, watchpoint
);
2400 xscale
->dbr_available
++;
2405 void xscale_enable_watchpoints(struct target_s
*target
)
2407 watchpoint_t
*watchpoint
= target
->watchpoints
;
2411 if (watchpoint
->set
== 0)
2412 xscale_set_watchpoint(target
, watchpoint
);
2413 watchpoint
= watchpoint
->next
;
2417 void xscale_enable_breakpoints(struct target_s
*target
)
2419 breakpoint_t
*breakpoint
= target
->breakpoints
;
2421 /* set any pending breakpoints */
2424 if (breakpoint
->set
== 0)
2425 xscale_set_breakpoint(target
, breakpoint
);
2426 breakpoint
= breakpoint
->next
;
2430 int xscale_get_reg(reg_t
*reg
)
2432 xscale_reg_t
*arch_info
= reg
->arch_info
;
2433 target_t
*target
= arch_info
->target
;
2434 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2435 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2437 /* DCSR, TX and RX are accessible via JTAG */
2438 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2440 return xscale_read_dcsr(arch_info
->target
);
2442 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2444 /* 1 = consume register content */
2445 return xscale_read_tx(arch_info
->target
, 1);
2447 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2449 /* can't read from RX register (host -> debug handler) */
2452 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2454 /* can't (explicitly) read from TXRXCTRL register */
2457 else /* Other DBG registers have to be transfered by the debug handler */
2459 /* send CP read request (command 0x40) */
2460 xscale_send_u32(target
, 0x40);
2462 /* send CP register number */
2463 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2465 /* read register value */
2466 xscale_read_tx(target
, 1);
2467 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2476 int xscale_set_reg(reg_t
*reg
, u8
* buf
)
2478 xscale_reg_t
*arch_info
= reg
->arch_info
;
2479 target_t
*target
= arch_info
->target
;
2480 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2481 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2482 u32 value
= buf_get_u32(buf
, 0, 32);
2484 /* DCSR, TX and RX are accessible via JTAG */
2485 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2487 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2488 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2490 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2492 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2493 return xscale_write_rx(arch_info
->target
);
2495 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2497 /* can't write to TX register (debug-handler -> host) */
2500 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2502 /* can't (explicitly) write to TXRXCTRL register */
2505 else /* Other DBG registers have to be transfered by the debug handler */
2507 /* send CP write request (command 0x41) */
2508 xscale_send_u32(target
, 0x41);
2510 /* send CP register number */
2511 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2513 /* send CP register value */
2514 xscale_send_u32(target
, value
);
2515 buf_set_u32(reg
->value
, 0, 32, value
);
2521 /* convenience wrapper to access XScale specific registers */
2522 int xscale_set_reg_u32(reg_t
*reg
, u32 value
)
2526 buf_set_u32(buf
, 0, 32, value
);
2528 return xscale_set_reg(reg
, buf
);
2531 int xscale_write_dcsr_sw(target_t
*target
, u32 value
)
2533 /* get pointers to arch-specific information */
2534 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2535 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2536 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2537 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2539 /* send CP write request (command 0x41) */
2540 xscale_send_u32(target
, 0x41);
2542 /* send CP register number */
2543 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2545 /* send CP register value */
2546 xscale_send_u32(target
, value
);
2547 buf_set_u32(dcsr
->value
, 0, 32, value
);
2552 int xscale_read_trace(target_t
*target
)
2554 /* get pointers to arch-specific information */
2555 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2556 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2557 xscale_trace_data_t
**trace_data_p
;
2559 /* 258 words from debug handler
2560 * 256 trace buffer entries
2561 * 2 checkpoint addresses
2563 u32 trace_buffer
[258];
2564 int is_address
[256];
2567 if (target
->state
!= TARGET_HALTED
)
2569 WARNING("target must be stopped to read trace data");
2570 return ERROR_TARGET_NOT_HALTED
;
2573 /* send read trace buffer command (command 0x61) */
2574 xscale_send_u32(target
, 0x61);
2576 /* receive trace buffer content */
2577 xscale_receive(target
, trace_buffer
, 258);
2579 /* parse buffer backwards to identify address entries */
2580 for (i
= 255; i
>= 0; i
--)
2583 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2584 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2587 is_address
[--i
] = 1;
2589 is_address
[--i
] = 1;
2591 is_address
[--i
] = 1;
2593 is_address
[--i
] = 1;
2598 /* search first non-zero entry */
2599 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2604 DEBUG("no trace data collected");
2605 return ERROR_XSCALE_NO_TRACE_DATA
;
2608 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2611 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2612 (*trace_data_p
)->next
= NULL
;
2613 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2614 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2615 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2616 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2617 (*trace_data_p
)->depth
= 256 - j
;
2619 for (i
= j
; i
< 256; i
++)
2621 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2623 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2625 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2631 int xscale_read_instruction(target_t
*target
, arm_instruction_t
*instruction
)
2633 /* get pointers to arch-specific information */
2634 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2635 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2642 if (!xscale
->trace
.image
)
2643 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2645 /* search for the section the current instruction belongs to */
2646 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2648 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2649 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2658 /* current instruction couldn't be found in the image */
2659 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2662 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2665 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2666 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2667 4, buf
, &size_read
)) != ERROR_OK
)
2669 ERROR("error while reading instruction: %i", retval
);
2670 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2672 opcode
= target_buffer_get_u32(target
, buf
);
2673 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2675 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2678 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2679 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2680 2, buf
, &size_read
)) != ERROR_OK
)
2682 ERROR("error while reading instruction: %i", retval
);
2683 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2685 opcode
= target_buffer_get_u16(target
, buf
);
2686 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2690 ERROR("BUG: unknown core state encountered");
2697 int xscale_branch_address(xscale_trace_data_t
*trace_data
, int i
, u32
*target
)
2699 /* if there are less than four entries prior to the indirect branch message
2700 * we can't extract the address */
2706 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2707 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2712 int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2714 /* get pointers to arch-specific information */
2715 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2716 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2719 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2728 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2733 for (i
= 0; i
< trace_data
->depth
; i
++)
2739 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2742 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2744 case 0: /* Exceptions */
2752 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2754 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2755 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2757 case 8: /* Direct Branch */
2760 case 9: /* Indirect Branch */
2762 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2767 case 13: /* Checkpointed Indirect Branch */
2768 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2771 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2772 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2773 WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2775 /* explicit fall-through */
2776 case 12: /* Checkpointed Direct Branch */
2781 next_pc
= trace_data
->chkpt0
;
2784 else if (chkpt
== 1)
2787 next_pc
= trace_data
->chkpt0
;
2792 WARNING("more than two checkpointed branches encountered");
2795 case 15: /* Roll-over */
2798 default: /* Reserved */
2799 command_print(cmd_ctx
, "--- reserved trace message ---");
2800 ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2804 if (xscale
->trace
.pc_ok
)
2806 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2807 arm_instruction_t instruction
;
2809 if ((exception
== 6) || (exception
== 7))
2811 /* IRQ or FIQ exception, no instruction executed */
2815 while (executed
-- >= 0)
2817 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2819 /* can't continue tracing with no image available */
2820 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2824 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2826 /* TODO: handle incomplete images */
2830 /* a precise abort on a load to the PC is included in the incremental
2831 * word count, other instructions causing data aborts are not included
2833 if ((executed
== 0) && (exception
== 4)
2834 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2836 if ((instruction
.type
== ARM_LDM
)
2837 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2841 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2842 && (instruction
.info
.load_store
.Rd
!= 15))
2848 /* only the last instruction executed
2849 * (the one that caused the control flow change)
2850 * could be a taken branch
2852 if (((executed
== -1) && (branch
== 1)) &&
2853 (((instruction
.type
== ARM_B
) ||
2854 (instruction
.type
== ARM_BL
) ||
2855 (instruction
.type
== ARM_BLX
)) &&
2856 (instruction
.info
.b_bl_bx_blx
.target_address
!= -1)))
2858 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2862 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2864 command_print(cmd_ctx
, "%s", instruction
.text
);
2872 xscale
->trace
.current_pc
= next_pc
;
2873 xscale
->trace
.pc_ok
= 1;
2877 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2879 arm_instruction_t instruction
;
2880 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2882 /* can't continue tracing with no image available */
2883 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2887 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2889 /* TODO: handle incomplete images */
2892 command_print(cmd_ctx
, "%s", instruction
.text
);
2895 trace_data
= trace_data
->next
;
2901 void xscale_build_reg_cache(target_t
*target
)
2903 /* get pointers to arch-specific information */
2904 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2905 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2907 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2908 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2910 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2912 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2913 armv4_5
->core_cache
= (*cache_p
);
2915 /* register a register arch-type for XScale dbg registers only once */
2916 if (xscale_reg_arch_type
== -1)
2917 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
2919 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
2920 cache_p
= &(*cache_p
)->next
;
2922 /* fill in values for the xscale reg cache */
2923 (*cache_p
)->name
= "XScale registers";
2924 (*cache_p
)->next
= NULL
;
2925 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
2926 (*cache_p
)->num_regs
= num_regs
;
2928 for (i
= 0; i
< num_regs
; i
++)
2930 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2931 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2932 (*cache_p
)->reg_list
[i
].dirty
= 0;
2933 (*cache_p
)->reg_list
[i
].valid
= 0;
2934 (*cache_p
)->reg_list
[i
].size
= 32;
2935 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
2936 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
2937 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2938 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
2939 arch_info
[i
] = xscale_reg_arch_info
[i
];
2940 arch_info
[i
].target
= target
;
2943 xscale
->reg_cache
= (*cache_p
);
2946 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
2948 if (startup_mode
!= DAEMON_RESET
)
2950 ERROR("XScale target requires a reset");
2951 ERROR("Reset target to enable debug");
2954 /* assert TRST once during startup */
2955 jtag_add_reset(1, 0);
2956 jtag_add_sleep(5000);
2957 jtag_add_reset(0, 0);
2958 jtag_execute_queue();
2969 int xscale_init_arch_info(target_t
*target
, xscale_common_t
*xscale
, int chain_pos
, char *variant
)
2971 armv4_5_common_t
*armv4_5
;
2972 u32 high_reset_branch
, low_reset_branch
;
2975 armv4_5
= &xscale
->armv4_5_common
;
2977 /* store architecture specfic data (none so far) */
2978 xscale
->arch_info
= NULL
;
2979 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
2981 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
2982 xscale
->variant
= strdup(variant
);
2984 /* prepare JTAG information for the new target */
2985 xscale
->jtag_info
.chain_pos
= chain_pos
;
2986 jtag_register_event_callback(xscale_jtag_callback
, target
);
2988 xscale
->jtag_info
.dbgrx
= 0x02;
2989 xscale
->jtag_info
.dbgtx
= 0x10;
2990 xscale
->jtag_info
.dcsr
= 0x09;
2991 xscale
->jtag_info
.ldic
= 0x07;
2993 if ((strcmp(xscale
->variant
, "pxa250") == 0) ||
2994 (strcmp(xscale
->variant
, "pxa255") == 0) ||
2995 (strcmp(xscale
->variant
, "pxa26x") == 0))
2997 xscale
->jtag_info
.ir_length
= 5;
2999 else if ((strcmp(xscale
->variant
, "pxa27x") == 0) ||
3000 (strcmp(xscale
->variant
, "ixp42x") == 0) ||
3001 (strcmp(xscale
->variant
, "ixp45x") == 0) ||
3002 (strcmp(xscale
->variant
, "ixp46x") == 0))
3004 xscale
->jtag_info
.ir_length
= 7;
3007 /* the debug handler isn't installed (and thus not running) at this time */
3008 xscale
->handler_installed
= 0;
3009 xscale
->handler_running
= 0;
3010 xscale
->handler_address
= 0xfe000800;
3012 /* clear the vectors we keep locally for reference */
3013 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
3014 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
3016 /* no user-specified vectors have been configured yet */
3017 xscale
->static_low_vectors_set
= 0x0;
3018 xscale
->static_high_vectors_set
= 0x0;
3020 /* calculate branches to debug handler */
3021 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
3022 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3024 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3025 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3027 for (i
= 1; i
<= 7; i
++)
3029 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3030 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3033 /* 64kB aligned region used for DCache cleaning */
3034 xscale
->cache_clean_address
= 0xfffe0000;
3036 xscale
->hold_rst
= 0;
3037 xscale
->external_debug_break
= 0;
3039 xscale
->force_hw_bkpts
= 1;
3041 xscale
->ibcr_available
= 2;
3042 xscale
->ibcr0_used
= 0;
3043 xscale
->ibcr1_used
= 0;
3045 xscale
->dbr_available
= 2;
3046 xscale
->dbr0_used
= 0;
3047 xscale
->dbr1_used
= 0;
3049 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3050 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3052 xscale
->vector_catch
= 0x1;
3054 xscale
->trace
.capture_status
= TRACE_IDLE
;
3055 xscale
->trace
.data
= NULL
;
3056 xscale
->trace
.image
= NULL
;
3057 xscale
->trace
.buffer_enabled
= 0;
3058 xscale
->trace
.buffer_fill
= 0;
3060 /* prepare ARMv4/5 specific information */
3061 armv4_5
->arch_info
= xscale
;
3062 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3063 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3064 armv4_5
->full_context
= xscale_full_context
;
3066 armv4_5_init_arch_info(target
, armv4_5
);
3068 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3069 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3070 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3071 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3072 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3073 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3074 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3075 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3080 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3081 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
3084 char *variant
= NULL
;
3085 xscale_common_t
*xscale
= malloc(sizeof(xscale_common_t
));
3089 ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
3093 chain_pos
= strtoul(args
[3], NULL
, 0);
3097 xscale_init_arch_info(target
, xscale
, chain_pos
, variant
);
3098 xscale_build_reg_cache(target
);
3103 int xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3105 target_t
*target
= NULL
;
3106 armv4_5_common_t
*armv4_5
;
3107 xscale_common_t
*xscale
;
3109 u32 handler_address
;
3113 ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3117 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3119 ERROR("no target '%s' configured", args
[0]);
3123 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3125 command_print(cmd_ctx
, "target isn't an ARM920t target");
3129 handler_address
= strtoul(args
[1], NULL
, 0);
3131 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3132 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3134 xscale
->handler_address
= handler_address
;
3138 ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3144 int xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3146 target_t
*target
= NULL
;
3147 armv4_5_common_t
*armv4_5
;
3148 xscale_common_t
*xscale
;
3150 u32 cache_clean_address
;
3154 ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3158 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3160 ERROR("no target '%s' configured", args
[0]);
3164 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3166 command_print(cmd_ctx
, "target isn't an XScale target");
3170 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3172 if (cache_clean_address
& 0xffff)
3174 ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3178 xscale
->cache_clean_address
= cache_clean_address
;
3184 int xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3186 target_t
*target
= get_current_target(cmd_ctx
);
3187 armv4_5_common_t
*armv4_5
;
3188 xscale_common_t
*xscale
;
3190 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3192 command_print(cmd_ctx
, "target isn't an XScale target");
3196 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3199 int xscale_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3201 target_t
*target
= get_current_target(cmd_ctx
);
3202 armv4_5_common_t
*armv4_5
;
3203 xscale_common_t
*xscale
;
3205 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3207 command_print(cmd_ctx
, "target isn't an XScale target");
3211 if (target
->state
!= TARGET_HALTED
)
3213 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3217 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &xscale
->armv4_5_mmu
);
3220 int xscale_handle_mmu_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3222 target_t
*target
= get_current_target(cmd_ctx
);
3223 armv4_5_common_t
*armv4_5
;
3224 xscale_common_t
*xscale
;
3226 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3228 command_print(cmd_ctx
, "target isn't an XScale target");
3232 if (target
->state
!= TARGET_HALTED
)
3234 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3240 if (strcmp("enable", args
[0]) == 0)
3242 xscale_enable_mmu_caches(target
, 1, 0, 0);
3243 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3245 else if (strcmp("disable", args
[0]) == 0)
3247 xscale_disable_mmu_caches(target
, 1, 0, 0);
3248 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3252 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3257 int xscale_handle_idcache_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3259 target_t
*target
= get_current_target(cmd_ctx
);
3260 armv4_5_common_t
*armv4_5
;
3261 xscale_common_t
*xscale
;
3262 int icache
= 0, dcache
= 0;
3264 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3266 command_print(cmd_ctx
, "target isn't an XScale target");
3270 if (target
->state
!= TARGET_HALTED
)
3272 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3276 if (strcmp(cmd
, "icache") == 0)
3278 else if (strcmp(cmd
, "dcache") == 0)
3283 if (strcmp("enable", args
[0]) == 0)
3285 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3288 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3290 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3292 else if (strcmp("disable", args
[0]) == 0)
3294 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3297 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3299 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3304 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3307 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3312 int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3314 target_t
*target
= get_current_target(cmd_ctx
);
3315 armv4_5_common_t
*armv4_5
;
3316 xscale_common_t
*xscale
;
3318 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3320 command_print(cmd_ctx
, "target isn't an XScale target");
3326 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3330 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3331 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3332 xscale_write_dcsr(target
, -1, -1);
3335 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3340 int xscale_handle_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3342 target_t
*target
= get_current_target(cmd_ctx
);
3343 armv4_5_common_t
*armv4_5
;
3344 xscale_common_t
*xscale
;
3346 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3348 command_print(cmd_ctx
, "target isn't an XScale target");
3352 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3354 xscale
->force_hw_bkpts
= 1;
3356 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3358 xscale
->force_hw_bkpts
= 0;
3362 command_print(cmd_ctx
, "usage: xscale force_hw_bkpts <enable|disable>");
3365 command_print(cmd_ctx
, "force hardware breakpoints %s", (xscale
->force_hw_bkpts
) ? "enabled" : "disabled");
3370 int xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3372 target_t
*target
= get_current_target(cmd_ctx
);
3373 armv4_5_common_t
*armv4_5
;
3374 xscale_common_t
*xscale
;
3377 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3379 command_print(cmd_ctx
, "target isn't an XScale target");
3383 if (target
->state
!= TARGET_HALTED
)
3385 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3389 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3391 xscale_trace_data_t
*td
, *next_td
;
3392 xscale
->trace
.buffer_enabled
= 1;
3394 /* free old trace data */
3395 td
= xscale
->trace
.data
;
3405 xscale
->trace
.data
= NULL
;
3407 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3409 xscale
->trace
.buffer_enabled
= 0;
3412 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3415 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3417 xscale
->trace
.buffer_fill
= 1;
3419 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3421 xscale
->trace
.buffer_fill
= -1;
3424 if (xscale
->trace
.buffer_enabled
)
3426 /* if we enable the trace buffer in fill-once
3427 * mode we know the address of the first instruction */
3428 xscale
->trace
.pc_ok
= 1;
3429 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3433 /* otherwise the address is unknown, and we have no known good PC */
3434 xscale
->trace
.pc_ok
= 0;
3437 command_print(cmd_ctx
, "trace buffer %s (%s)",
3438 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3439 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3441 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3442 if (xscale
->trace
.buffer_fill
>= 0)
3443 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3445 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3450 int xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3453 armv4_5_common_t
*armv4_5
;
3454 xscale_common_t
*xscale
;
3458 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3462 target
= get_current_target(cmd_ctx
);
3464 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3466 command_print(cmd_ctx
, "target isn't an XScale target");
3470 if (xscale
->trace
.image
)
3472 image_close(xscale
->trace
.image
);
3473 free(xscale
->trace
.image
);
3474 command_print(cmd_ctx
, "previously loaded image found and closed");
3477 xscale
->trace
.image
= malloc(sizeof(image_t
));
3478 xscale
->trace
.image
->base_address_set
= 0;
3479 xscale
->trace
.image
->start_address_set
= 0;
3481 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3484 xscale
->trace
.image
->base_address_set
= 1;
3485 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3489 xscale
->trace
.image
->base_address_set
= 0;
3492 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3494 command_print(cmd_ctx
, "image opening error: %s", xscale
->trace
.image
->error_str
);
3495 free(xscale
->trace
.image
);
3496 xscale
->trace
.image
= NULL
;
3503 int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3505 target_t
*target
= get_current_target(cmd_ctx
);
3506 armv4_5_common_t
*armv4_5
;
3507 xscale_common_t
*xscale
;
3508 xscale_trace_data_t
*trace_data
;
3511 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3513 command_print(cmd_ctx
, "target isn't an XScale target");
3517 if (target
->state
!= TARGET_HALTED
)
3519 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3525 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3529 trace_data
= xscale
->trace
.data
;
3533 command_print(cmd_ctx
, "no trace data collected");
3537 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3539 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
3547 fileio_write_u32(&file
, trace_data
->chkpt0
);
3548 fileio_write_u32(&file
, trace_data
->chkpt1
);
3549 fileio_write_u32(&file
, trace_data
->last_instruction
);
3550 fileio_write_u32(&file
, trace_data
->depth
);
3552 for (i
= 0; i
< trace_data
->depth
; i
++)
3553 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3555 trace_data
= trace_data
->next
;
3558 fileio_close(&file
);
3563 int xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3565 target_t
*target
= get_current_target(cmd_ctx
);
3566 armv4_5_common_t
*armv4_5
;
3567 xscale_common_t
*xscale
;
3569 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3571 command_print(cmd_ctx
, "target isn't an XScale target");
3575 xscale_analyze_trace(target
, cmd_ctx
);
3580 int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3582 command_t
*xscale_cmd
;
3584 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3586 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_CONFIG
, NULL
);
3587 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3589 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3590 register_command(cmd_ctx
, xscale_cmd
, "virt2phys", xscale_handle_virt2phys_command
, COMMAND_EXEC
, NULL
);
3591 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3592 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3593 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3595 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_idcache_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3597 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable|disable> ['fill' [n]|'wrap']");
3599 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3600 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3601 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3602 COMMAND_EXEC
, "load image from <file> [base address]");
3604 armv4_5_register_commands(cmd_ctx
);
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