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xscale: mark xscale registers invalid on debug entry
[openocd.git] / src / target / xscale.c
1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "breakpoints.h"
31 #include "xscale.h"
32 #include "target_type.h"
33 #include "arm_jtag.h"
34 #include "arm_simulator.h"
35 #include "arm_disassembler.h"
36 #include <helper/time_support.h>
37 #include "register.h"
38 #include "image.h"
39 #include "arm_opcodes.h"
40 #include "armv4_5.h"
41
42
43 /*
44 * Important XScale documents available as of October 2009 include:
45 *
46 * Intel XScale® Core Developer’s Manual, January 2004
47 * Order Number: 273473-002
48 * This has a chapter detailing debug facilities, and punts some
49 * details to chip-specific microarchitecture documents.
50 *
51 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
52 * Document Number: 273539-005
53 * Less detailed than the developer's manual, but summarizes those
54 * missing details (for most XScales) and gives LOTS of notes about
55 * debugger/handler interaction issues. Presents a simpler reset
56 * and load-handler sequence than the arch doc. (Note, OpenOCD
57 * doesn't currently support "Hot-Debug" as defined there.)
58 *
59 * Chip-specific microarchitecture documents may also be useful.
60 */
61
62
63 /* forward declarations */
64 static int xscale_resume(struct target *, int current,
65 uint32_t address, int handle_breakpoints, int debug_execution);
66 static int xscale_debug_entry(struct target *);
67 static int xscale_restore_banked(struct target *);
68 static int xscale_get_reg(struct reg *reg);
69 static int xscale_set_reg(struct reg *reg, uint8_t *buf);
70 static int xscale_set_breakpoint(struct target *, struct breakpoint *);
71 static int xscale_set_watchpoint(struct target *, struct watchpoint *);
72 static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
73 static int xscale_read_trace(struct target *);
74
75
76 /* This XScale "debug handler" is loaded into the processor's
77 * mini-ICache, which is 2K of code writable only via JTAG.
78 *
79 * FIXME the OpenOCD "bin2char" utility currently doesn't handle
80 * binary files cleanly. It's string oriented, and terminates them
81 * with a NUL character. Better would be to generate the constants
82 * and let other code decide names, scoping, and other housekeeping.
83 */
84 static /* unsigned const char xscale_debug_handler[] = ... */
85 #include "xscale_debug.h"
86
87 static char *const xscale_reg_list[] =
88 {
89 "XSCALE_MAINID", /* 0 */
90 "XSCALE_CACHETYPE",
91 "XSCALE_CTRL",
92 "XSCALE_AUXCTRL",
93 "XSCALE_TTB",
94 "XSCALE_DAC",
95 "XSCALE_FSR",
96 "XSCALE_FAR",
97 "XSCALE_PID",
98 "XSCALE_CPACCESS",
99 "XSCALE_IBCR0", /* 10 */
100 "XSCALE_IBCR1",
101 "XSCALE_DBR0",
102 "XSCALE_DBR1",
103 "XSCALE_DBCON",
104 "XSCALE_TBREG",
105 "XSCALE_CHKPT0",
106 "XSCALE_CHKPT1",
107 "XSCALE_DCSR",
108 "XSCALE_TX",
109 "XSCALE_RX", /* 20 */
110 "XSCALE_TXRXCTRL",
111 };
112
113 static const struct xscale_reg xscale_reg_arch_info[] =
114 {
115 {XSCALE_MAINID, NULL},
116 {XSCALE_CACHETYPE, NULL},
117 {XSCALE_CTRL, NULL},
118 {XSCALE_AUXCTRL, NULL},
119 {XSCALE_TTB, NULL},
120 {XSCALE_DAC, NULL},
121 {XSCALE_FSR, NULL},
122 {XSCALE_FAR, NULL},
123 {XSCALE_PID, NULL},
124 {XSCALE_CPACCESS, NULL},
125 {XSCALE_IBCR0, NULL},
126 {XSCALE_IBCR1, NULL},
127 {XSCALE_DBR0, NULL},
128 {XSCALE_DBR1, NULL},
129 {XSCALE_DBCON, NULL},
130 {XSCALE_TBREG, NULL},
131 {XSCALE_CHKPT0, NULL},
132 {XSCALE_CHKPT1, NULL},
133 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
134 {-1, NULL}, /* TX accessed via JTAG */
135 {-1, NULL}, /* RX accessed via JTAG */
136 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
137 };
138
139 /* convenience wrapper to access XScale specific registers */
140 static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
141 {
142 uint8_t buf[4];
143
144 buf_set_u32(buf, 0, 32, value);
145
146 return xscale_set_reg(reg, buf);
147 }
148
149 static const char xscale_not[] = "target is not an XScale";
150
151 static int xscale_verify_pointer(struct command_context *cmd_ctx,
152 struct xscale_common *xscale)
153 {
154 if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
155 command_print(cmd_ctx, xscale_not);
156 return ERROR_TARGET_INVALID;
157 }
158 return ERROR_OK;
159 }
160
161 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
162 {
163 assert (tap != NULL);
164
165 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
166 {
167 struct scan_field field;
168 uint8_t scratch[4];
169
170 memset(&field, 0, sizeof field);
171 field.num_bits = tap->ir_length;
172 field.out_value = scratch;
173 buf_set_u32(scratch, 0, field.num_bits, new_instr);
174
175 jtag_add_ir_scan(tap, &field, end_state);
176 }
177
178 return ERROR_OK;
179 }
180
181 static int xscale_read_dcsr(struct target *target)
182 {
183 struct xscale_common *xscale = target_to_xscale(target);
184 int retval;
185 struct scan_field fields[3];
186 uint8_t field0 = 0x0;
187 uint8_t field0_check_value = 0x2;
188 uint8_t field0_check_mask = 0x7;
189 uint8_t field2 = 0x0;
190 uint8_t field2_check_value = 0x0;
191 uint8_t field2_check_mask = 0x1;
192
193 xscale_jtag_set_instr(target->tap,
194 XSCALE_SELDCSR << xscale->xscale_variant,
195 TAP_DRPAUSE);
196
197 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
198 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
199
200 memset(&fields, 0, sizeof fields);
201
202 fields[0].num_bits = 3;
203 fields[0].out_value = &field0;
204 uint8_t tmp;
205 fields[0].in_value = &tmp;
206
207 fields[1].num_bits = 32;
208 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
209
210 fields[2].num_bits = 1;
211 fields[2].out_value = &field2;
212 uint8_t tmp2;
213 fields[2].in_value = &tmp2;
214
215 jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
216
217 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
218 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
219
220 if ((retval = jtag_execute_queue()) != ERROR_OK)
221 {
222 LOG_ERROR("JTAG error while reading DCSR");
223 return retval;
224 }
225
226 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
227 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
228
229 /* write the register with the value we just read
230 * on this second pass, only the first bit of field0 is guaranteed to be 0)
231 */
232 field0_check_mask = 0x1;
233 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
234 fields[1].in_value = NULL;
235
236 jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
237
238 /* DANGER!!! this must be here. It will make sure that the arguments
239 * to jtag_set_check_value() does not go out of scope! */
240 return jtag_execute_queue();
241 }
242
243
244 static void xscale_getbuf(jtag_callback_data_t arg)
245 {
246 uint8_t *in = (uint8_t *)arg;
247 *((uint32_t *)in) = buf_get_u32(in, 0, 32);
248 }
249
250 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
251 {
252 if (num_words == 0)
253 return ERROR_INVALID_ARGUMENTS;
254
255 struct xscale_common *xscale = target_to_xscale(target);
256 int retval = ERROR_OK;
257 tap_state_t path[3];
258 struct scan_field fields[3];
259 uint8_t *field0 = malloc(num_words * 1);
260 uint8_t field0_check_value = 0x2;
261 uint8_t field0_check_mask = 0x6;
262 uint32_t *field1 = malloc(num_words * 4);
263 uint8_t field2_check_value = 0x0;
264 uint8_t field2_check_mask = 0x1;
265 int words_done = 0;
266 int words_scheduled = 0;
267 int i;
268
269 path[0] = TAP_DRSELECT;
270 path[1] = TAP_DRCAPTURE;
271 path[2] = TAP_DRSHIFT;
272
273 memset(&fields, 0, sizeof fields);
274
275 fields[0].num_bits = 3;
276 fields[0].check_value = &field0_check_value;
277 fields[0].check_mask = &field0_check_mask;
278
279 fields[1].num_bits = 32;
280
281 fields[2].num_bits = 1;
282 fields[2].check_value = &field2_check_value;
283 fields[2].check_mask = &field2_check_mask;
284
285 xscale_jtag_set_instr(target->tap,
286 XSCALE_DBGTX << xscale->xscale_variant,
287 TAP_IDLE);
288 jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
289
290 /* repeat until all words have been collected */
291 int attempts = 0;
292 while (words_done < num_words)
293 {
294 /* schedule reads */
295 words_scheduled = 0;
296 for (i = words_done; i < num_words; i++)
297 {
298 fields[0].in_value = &field0[i];
299
300 jtag_add_pathmove(3, path);
301
302 fields[1].in_value = (uint8_t *)(field1 + i);
303
304 jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
305
306 jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
307
308 words_scheduled++;
309 }
310
311 if ((retval = jtag_execute_queue()) != ERROR_OK)
312 {
313 LOG_ERROR("JTAG error while receiving data from debug handler");
314 break;
315 }
316
317 /* examine results */
318 for (i = words_done; i < num_words; i++)
319 {
320 if (!(field0[0] & 1))
321 {
322 /* move backwards if necessary */
323 int j;
324 for (j = i; j < num_words - 1; j++)
325 {
326 field0[j] = field0[j + 1];
327 field1[j] = field1[j + 1];
328 }
329 words_scheduled--;
330 }
331 }
332 if (words_scheduled == 0)
333 {
334 if (attempts++==1000)
335 {
336 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
337 retval = ERROR_TARGET_TIMEOUT;
338 break;
339 }
340 }
341
342 words_done += words_scheduled;
343 }
344
345 for (i = 0; i < num_words; i++)
346 *(buffer++) = buf_get_u32((uint8_t*)&field1[i], 0, 32);
347
348 free(field1);
349
350 return retval;
351 }
352
353 static int xscale_read_tx(struct target *target, int consume)
354 {
355 struct xscale_common *xscale = target_to_xscale(target);
356 tap_state_t path[3];
357 tap_state_t noconsume_path[6];
358 int retval;
359 struct timeval timeout, now;
360 struct scan_field fields[3];
361 uint8_t field0_in = 0x0;
362 uint8_t field0_check_value = 0x2;
363 uint8_t field0_check_mask = 0x6;
364 uint8_t field2_check_value = 0x0;
365 uint8_t field2_check_mask = 0x1;
366
367 xscale_jtag_set_instr(target->tap,
368 XSCALE_DBGTX << xscale->xscale_variant,
369 TAP_IDLE);
370
371 path[0] = TAP_DRSELECT;
372 path[1] = TAP_DRCAPTURE;
373 path[2] = TAP_DRSHIFT;
374
375 noconsume_path[0] = TAP_DRSELECT;
376 noconsume_path[1] = TAP_DRCAPTURE;
377 noconsume_path[2] = TAP_DREXIT1;
378 noconsume_path[3] = TAP_DRPAUSE;
379 noconsume_path[4] = TAP_DREXIT2;
380 noconsume_path[5] = TAP_DRSHIFT;
381
382 memset(&fields, 0, sizeof fields);
383
384 fields[0].num_bits = 3;
385 fields[0].in_value = &field0_in;
386
387 fields[1].num_bits = 32;
388 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
389
390 fields[2].num_bits = 1;
391 uint8_t tmp;
392 fields[2].in_value = &tmp;
393
394 gettimeofday(&timeout, NULL);
395 timeval_add_time(&timeout, 1, 0);
396
397 for (;;)
398 {
399 /* if we want to consume the register content (i.e. clear TX_READY),
400 * we have to go straight from Capture-DR to Shift-DR
401 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
402 */
403 if (consume)
404 jtag_add_pathmove(3, path);
405 else
406 {
407 jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
408 }
409
410 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
411
412 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
413 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
414
415 if ((retval = jtag_execute_queue()) != ERROR_OK)
416 {
417 LOG_ERROR("JTAG error while reading TX");
418 return ERROR_TARGET_TIMEOUT;
419 }
420
421 gettimeofday(&now, NULL);
422 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
423 {
424 LOG_ERROR("time out reading TX register");
425 return ERROR_TARGET_TIMEOUT;
426 }
427 if (!((!(field0_in & 1)) && consume))
428 {
429 goto done;
430 }
431 if (debug_level >= 3)
432 {
433 LOG_DEBUG("waiting 100ms");
434 alive_sleep(100); /* avoid flooding the logs */
435 } else
436 {
437 keep_alive();
438 }
439 }
440 done:
441
442 if (!(field0_in & 1))
443 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
444
445 return ERROR_OK;
446 }
447
448 static int xscale_write_rx(struct target *target)
449 {
450 struct xscale_common *xscale = target_to_xscale(target);
451 int retval;
452 struct timeval timeout, now;
453 struct scan_field fields[3];
454 uint8_t field0_out = 0x0;
455 uint8_t field0_in = 0x0;
456 uint8_t field0_check_value = 0x2;
457 uint8_t field0_check_mask = 0x6;
458 uint8_t field2 = 0x0;
459 uint8_t field2_check_value = 0x0;
460 uint8_t field2_check_mask = 0x1;
461
462 xscale_jtag_set_instr(target->tap,
463 XSCALE_DBGRX << xscale->xscale_variant,
464 TAP_IDLE);
465
466 memset(&fields, 0, sizeof fields);
467
468 fields[0].num_bits = 3;
469 fields[0].out_value = &field0_out;
470 fields[0].in_value = &field0_in;
471
472 fields[1].num_bits = 32;
473 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
474
475 fields[2].num_bits = 1;
476 fields[2].out_value = &field2;
477 uint8_t tmp;
478 fields[2].in_value = &tmp;
479
480 gettimeofday(&timeout, NULL);
481 timeval_add_time(&timeout, 1, 0);
482
483 /* poll until rx_read is low */
484 LOG_DEBUG("polling RX");
485 for (;;)
486 {
487 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
488
489 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
490 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
491
492 if ((retval = jtag_execute_queue()) != ERROR_OK)
493 {
494 LOG_ERROR("JTAG error while writing RX");
495 return retval;
496 }
497
498 gettimeofday(&now, NULL);
499 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
500 {
501 LOG_ERROR("time out writing RX register");
502 return ERROR_TARGET_TIMEOUT;
503 }
504 if (!(field0_in & 1))
505 goto done;
506 if (debug_level >= 3)
507 {
508 LOG_DEBUG("waiting 100ms");
509 alive_sleep(100); /* avoid flooding the logs */
510 } else
511 {
512 keep_alive();
513 }
514 }
515 done:
516
517 /* set rx_valid */
518 field2 = 0x1;
519 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
520
521 if ((retval = jtag_execute_queue()) != ERROR_OK)
522 {
523 LOG_ERROR("JTAG error while writing RX");
524 return retval;
525 }
526
527 return ERROR_OK;
528 }
529
530 /* send count elements of size byte to the debug handler */
531 static int xscale_send(struct target *target, uint8_t *buffer, int count, int size)
532 {
533 struct xscale_common *xscale = target_to_xscale(target);
534 uint32_t t[3];
535 int bits[3];
536 int retval;
537 int done_count = 0;
538
539 xscale_jtag_set_instr(target->tap,
540 XSCALE_DBGRX << xscale->xscale_variant,
541 TAP_IDLE);
542
543 bits[0]=3;
544 t[0]=0;
545 bits[1]=32;
546 t[2]=1;
547 bits[2]=1;
548 int endianness = target->endianness;
549 while (done_count++ < count)
550 {
551 switch (size)
552 {
553 case 4:
554 if (endianness == TARGET_LITTLE_ENDIAN)
555 {
556 t[1]=le_to_h_u32(buffer);
557 } else
558 {
559 t[1]=be_to_h_u32(buffer);
560 }
561 break;
562 case 2:
563 if (endianness == TARGET_LITTLE_ENDIAN)
564 {
565 t[1]=le_to_h_u16(buffer);
566 } else
567 {
568 t[1]=be_to_h_u16(buffer);
569 }
570 break;
571 case 1:
572 t[1]=buffer[0];
573 break;
574 default:
575 LOG_ERROR("BUG: size neither 4, 2 nor 1");
576 return ERROR_INVALID_ARGUMENTS;
577 }
578 jtag_add_dr_out(target->tap,
579 3,
580 bits,
581 t,
582 TAP_IDLE);
583 buffer += size;
584 }
585
586 if ((retval = jtag_execute_queue()) != ERROR_OK)
587 {
588 LOG_ERROR("JTAG error while sending data to debug handler");
589 return retval;
590 }
591
592 return ERROR_OK;
593 }
594
595 static int xscale_send_u32(struct target *target, uint32_t value)
596 {
597 struct xscale_common *xscale = target_to_xscale(target);
598
599 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
600 return xscale_write_rx(target);
601 }
602
603 static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
604 {
605 struct xscale_common *xscale = target_to_xscale(target);
606 int retval;
607 struct scan_field fields[3];
608 uint8_t field0 = 0x0;
609 uint8_t field0_check_value = 0x2;
610 uint8_t field0_check_mask = 0x7;
611 uint8_t field2 = 0x0;
612 uint8_t field2_check_value = 0x0;
613 uint8_t field2_check_mask = 0x1;
614
615 if (hold_rst != -1)
616 xscale->hold_rst = hold_rst;
617
618 if (ext_dbg_brk != -1)
619 xscale->external_debug_break = ext_dbg_brk;
620
621 xscale_jtag_set_instr(target->tap,
622 XSCALE_SELDCSR << xscale->xscale_variant,
623 TAP_IDLE);
624
625 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
626 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
627
628 memset(&fields, 0, sizeof fields);
629
630 fields[0].num_bits = 3;
631 fields[0].out_value = &field0;
632 uint8_t tmp;
633 fields[0].in_value = &tmp;
634
635 fields[1].num_bits = 32;
636 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
637
638 fields[2].num_bits = 1;
639 fields[2].out_value = &field2;
640 uint8_t tmp2;
641 fields[2].in_value = &tmp2;
642
643 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
644
645 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
646 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
647
648 if ((retval = jtag_execute_queue()) != ERROR_OK)
649 {
650 LOG_ERROR("JTAG error while writing DCSR");
651 return retval;
652 }
653
654 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
655 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
656
657 return ERROR_OK;
658 }
659
660 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
661 static unsigned int parity (unsigned int v)
662 {
663 // unsigned int ov = v;
664 v ^= v >> 16;
665 v ^= v >> 8;
666 v ^= v >> 4;
667 v &= 0xf;
668 // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
669 return (0x6996 >> v) & 1;
670 }
671
672 static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
673 {
674 struct xscale_common *xscale = target_to_xscale(target);
675 uint8_t packet[4];
676 uint8_t cmd;
677 int word;
678 struct scan_field fields[2];
679
680 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
681
682 /* LDIC into IR */
683 xscale_jtag_set_instr(target->tap,
684 XSCALE_LDIC << xscale->xscale_variant,
685 TAP_IDLE);
686
687 /* CMD is b011 to load a cacheline into the Mini ICache.
688 * Loading into the main ICache is deprecated, and unused.
689 * It's followed by three zero bits, and 27 address bits.
690 */
691 buf_set_u32(&cmd, 0, 6, 0x3);
692
693 /* virtual address of desired cache line */
694 buf_set_u32(packet, 0, 27, va >> 5);
695
696 memset(&fields, 0, sizeof fields);
697
698 fields[0].num_bits = 6;
699 fields[0].out_value = &cmd;
700
701 fields[1].num_bits = 27;
702 fields[1].out_value = packet;
703
704 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
705
706 /* rest of packet is a cacheline: 8 instructions, with parity */
707 fields[0].num_bits = 32;
708 fields[0].out_value = packet;
709
710 fields[1].num_bits = 1;
711 fields[1].out_value = &cmd;
712
713 for (word = 0; word < 8; word++)
714 {
715 buf_set_u32(packet, 0, 32, buffer[word]);
716
717 uint32_t value;
718 memcpy(&value, packet, sizeof(uint32_t));
719 cmd = parity(value);
720
721 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
722 }
723
724 return jtag_execute_queue();
725 }
726
727 static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
728 {
729 struct xscale_common *xscale = target_to_xscale(target);
730 uint8_t packet[4];
731 uint8_t cmd;
732 struct scan_field fields[2];
733
734 xscale_jtag_set_instr(target->tap,
735 XSCALE_LDIC << xscale->xscale_variant,
736 TAP_IDLE);
737
738 /* CMD for invalidate IC line b000, bits [6:4] b000 */
739 buf_set_u32(&cmd, 0, 6, 0x0);
740
741 /* virtual address of desired cache line */
742 buf_set_u32(packet, 0, 27, va >> 5);
743
744 memset(&fields, 0, sizeof fields);
745
746 fields[0].num_bits = 6;
747 fields[0].out_value = &cmd;
748
749 fields[1].num_bits = 27;
750 fields[1].out_value = packet;
751
752 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
753
754 return ERROR_OK;
755 }
756
757 static int xscale_update_vectors(struct target *target)
758 {
759 struct xscale_common *xscale = target_to_xscale(target);
760 int i;
761 int retval;
762
763 uint32_t low_reset_branch, high_reset_branch;
764
765 for (i = 1; i < 8; i++)
766 {
767 /* if there's a static vector specified for this exception, override */
768 if (xscale->static_high_vectors_set & (1 << i))
769 {
770 xscale->high_vectors[i] = xscale->static_high_vectors[i];
771 }
772 else
773 {
774 retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
775 if (retval == ERROR_TARGET_TIMEOUT)
776 return retval;
777 if (retval != ERROR_OK)
778 {
779 /* Some of these reads will fail as part of normal execution */
780 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
781 }
782 }
783 }
784
785 for (i = 1; i < 8; i++)
786 {
787 if (xscale->static_low_vectors_set & (1 << i))
788 {
789 xscale->low_vectors[i] = xscale->static_low_vectors[i];
790 }
791 else
792 {
793 retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
794 if (retval == ERROR_TARGET_TIMEOUT)
795 return retval;
796 if (retval != ERROR_OK)
797 {
798 /* Some of these reads will fail as part of normal execution */
799 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
800 }
801 }
802 }
803
804 /* calculate branches to debug handler */
805 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
806 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
807
808 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
809 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
810
811 /* invalidate and load exception vectors in mini i-cache */
812 xscale_invalidate_ic_line(target, 0x0);
813 xscale_invalidate_ic_line(target, 0xffff0000);
814
815 xscale_load_ic(target, 0x0, xscale->low_vectors);
816 xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
817
818 return ERROR_OK;
819 }
820
821 static int xscale_arch_state(struct target *target)
822 {
823 struct xscale_common *xscale = target_to_xscale(target);
824 struct arm *armv4_5 = &xscale->armv4_5_common;
825
826 static const char *state[] =
827 {
828 "disabled", "enabled"
829 };
830
831 static const char *arch_dbg_reason[] =
832 {
833 "", "\n(processor reset)", "\n(trace buffer full)"
834 };
835
836 if (armv4_5->common_magic != ARM_COMMON_MAGIC)
837 {
838 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
839 return ERROR_INVALID_ARGUMENTS;
840 }
841
842 arm_arch_state(target);
843 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
844 state[xscale->armv4_5_mmu.mmu_enabled],
845 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
846 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
847 arch_dbg_reason[xscale->arch_debug_reason]);
848
849 return ERROR_OK;
850 }
851
852 static int xscale_poll(struct target *target)
853 {
854 int retval = ERROR_OK;
855
856 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
857 {
858 enum target_state previous_state = target->state;
859 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
860 {
861
862 /* there's data to read from the tx register, we entered debug state */
863 target->state = TARGET_HALTED;
864
865 /* process debug entry, fetching current mode regs */
866 retval = xscale_debug_entry(target);
867 }
868 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
869 {
870 LOG_USER("error while polling TX register, reset CPU");
871 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
872 target->state = TARGET_HALTED;
873 }
874
875 /* debug_entry could have overwritten target state (i.e. immediate resume)
876 * don't signal event handlers in that case
877 */
878 if (target->state != TARGET_HALTED)
879 return ERROR_OK;
880
881 /* if target was running, signal that we halted
882 * otherwise we reentered from debug execution */
883 if (previous_state == TARGET_RUNNING)
884 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
885 else
886 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
887 }
888
889 return retval;
890 }
891
892 static int xscale_debug_entry(struct target *target)
893 {
894 struct xscale_common *xscale = target_to_xscale(target);
895 struct arm *armv4_5 = &xscale->armv4_5_common;
896 uint32_t pc;
897 uint32_t buffer[10];
898 unsigned i;
899 int retval;
900 uint32_t moe;
901
902 /* clear external dbg break (will be written on next DCSR read) */
903 xscale->external_debug_break = 0;
904 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
905 return retval;
906
907 /* get r0, pc, r1 to r7 and cpsr */
908 if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK)
909 return retval;
910
911 /* move r0 from buffer to register cache */
912 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
913 armv4_5->core_cache->reg_list[0].dirty = 1;
914 armv4_5->core_cache->reg_list[0].valid = 1;
915 LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
916
917 /* move pc from buffer to register cache */
918 buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]);
919 armv4_5->pc->dirty = 1;
920 armv4_5->pc->valid = 1;
921 LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
922
923 /* move data from buffer to register cache */
924 for (i = 1; i <= 7; i++)
925 {
926 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
927 armv4_5->core_cache->reg_list[i].dirty = 1;
928 armv4_5->core_cache->reg_list[i].valid = 1;
929 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
930 }
931
932 arm_set_cpsr(armv4_5, buffer[9]);
933 LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
934
935 if (!is_arm_mode(armv4_5->core_mode))
936 {
937 target->state = TARGET_UNKNOWN;
938 LOG_ERROR("cpsr contains invalid mode value - communication failure");
939 return ERROR_TARGET_FAILURE;
940 }
941 LOG_DEBUG("target entered debug state in %s mode",
942 arm_mode_name(armv4_5->core_mode));
943
944 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
945 if (armv4_5->spsr) {
946 xscale_receive(target, buffer, 8);
947 buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]);
948 armv4_5->spsr->dirty = false;
949 armv4_5->spsr->valid = true;
950 }
951 else
952 {
953 /* r8 to r14, but no spsr */
954 xscale_receive(target, buffer, 7);
955 }
956
957 /* move data from buffer to right banked register in cache */
958 for (i = 8; i <= 14; i++)
959 {
960 struct reg *r = arm_reg_current(armv4_5, i);
961
962 buf_set_u32(r->value, 0, 32, buffer[i - 8]);
963 r->dirty = false;
964 r->valid = true;
965 }
966
967 /* mark xscale regs invalid to ensure they are retrieved from the
968 * debug handler if requested */
969 for (i = 0; i < xscale->reg_cache->num_regs; i++)
970 xscale->reg_cache->reg_list[i].valid = 0;
971
972 /* examine debug reason */
973 xscale_read_dcsr(target);
974 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
975
976 /* stored PC (for calculating fixup) */
977 pc = buf_get_u32(armv4_5->pc->value, 0, 32);
978
979 switch (moe)
980 {
981 case 0x0: /* Processor reset */
982 target->debug_reason = DBG_REASON_DBGRQ;
983 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
984 pc -= 4;
985 break;
986 case 0x1: /* Instruction breakpoint hit */
987 target->debug_reason = DBG_REASON_BREAKPOINT;
988 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
989 pc -= 4;
990 break;
991 case 0x2: /* Data breakpoint hit */
992 target->debug_reason = DBG_REASON_WATCHPOINT;
993 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
994 pc -= 4;
995 break;
996 case 0x3: /* BKPT instruction executed */
997 target->debug_reason = DBG_REASON_BREAKPOINT;
998 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
999 pc -= 4;
1000 break;
1001 case 0x4: /* Ext. debug event */
1002 target->debug_reason = DBG_REASON_DBGRQ;
1003 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1004 pc -= 4;
1005 break;
1006 case 0x5: /* Vector trap occured */
1007 target->debug_reason = DBG_REASON_BREAKPOINT;
1008 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1009 pc -= 4;
1010 break;
1011 case 0x6: /* Trace buffer full break */
1012 target->debug_reason = DBG_REASON_DBGRQ;
1013 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1014 pc -= 4;
1015 break;
1016 case 0x7: /* Reserved (may flag Hot-Debug support) */
1017 default:
1018 LOG_ERROR("Method of Entry is 'Reserved'");
1019 exit(-1);
1020 break;
1021 }
1022
1023 /* apply PC fixup */
1024 buf_set_u32(armv4_5->pc->value, 0, 32, pc);
1025
1026 /* on the first debug entry, identify cache type */
1027 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1028 {
1029 uint32_t cache_type_reg;
1030
1031 /* read cp15 cache type register */
1032 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1033 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1034
1035 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1036 }
1037
1038 /* examine MMU and Cache settings */
1039 /* read cp15 control register */
1040 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1041 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1042 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1043 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1044 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1045
1046 /* tracing enabled, read collected trace data */
1047 if (xscale->trace.buffer_enabled)
1048 {
1049 xscale_read_trace(target);
1050 xscale->trace.buffer_fill--;
1051
1052 /* resume if we're still collecting trace data */
1053 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1054 && (xscale->trace.buffer_fill > 0))
1055 {
1056 xscale_resume(target, 1, 0x0, 1, 0);
1057 }
1058 else
1059 {
1060 xscale->trace.buffer_enabled = 0;
1061 }
1062 }
1063
1064 return ERROR_OK;
1065 }
1066
1067 static int xscale_halt(struct target *target)
1068 {
1069 struct xscale_common *xscale = target_to_xscale(target);
1070
1071 LOG_DEBUG("target->state: %s",
1072 target_state_name(target));
1073
1074 if (target->state == TARGET_HALTED)
1075 {
1076 LOG_DEBUG("target was already halted");
1077 return ERROR_OK;
1078 }
1079 else if (target->state == TARGET_UNKNOWN)
1080 {
1081 /* this must not happen for a xscale target */
1082 LOG_ERROR("target was in unknown state when halt was requested");
1083 return ERROR_TARGET_INVALID;
1084 }
1085 else if (target->state == TARGET_RESET)
1086 {
1087 LOG_DEBUG("target->state == TARGET_RESET");
1088 }
1089 else
1090 {
1091 /* assert external dbg break */
1092 xscale->external_debug_break = 1;
1093 xscale_read_dcsr(target);
1094
1095 target->debug_reason = DBG_REASON_DBGRQ;
1096 }
1097
1098 return ERROR_OK;
1099 }
1100
1101 static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
1102 {
1103 struct xscale_common *xscale = target_to_xscale(target);
1104 struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1105 int retval;
1106
1107 if (xscale->ibcr0_used)
1108 {
1109 struct breakpoint *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1110
1111 if (ibcr0_bp)
1112 {
1113 xscale_unset_breakpoint(target, ibcr0_bp);
1114 }
1115 else
1116 {
1117 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1118 exit(-1);
1119 }
1120 }
1121
1122 if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
1123 return retval;
1124
1125 return ERROR_OK;
1126 }
1127
1128 static int xscale_disable_single_step(struct target *target)
1129 {
1130 struct xscale_common *xscale = target_to_xscale(target);
1131 struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1132 int retval;
1133
1134 if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
1135 return retval;
1136
1137 return ERROR_OK;
1138 }
1139
1140 static void xscale_enable_watchpoints(struct target *target)
1141 {
1142 struct watchpoint *watchpoint = target->watchpoints;
1143
1144 while (watchpoint)
1145 {
1146 if (watchpoint->set == 0)
1147 xscale_set_watchpoint(target, watchpoint);
1148 watchpoint = watchpoint->next;
1149 }
1150 }
1151
1152 static void xscale_enable_breakpoints(struct target *target)
1153 {
1154 struct breakpoint *breakpoint = target->breakpoints;
1155
1156 /* set any pending breakpoints */
1157 while (breakpoint)
1158 {
1159 if (breakpoint->set == 0)
1160 xscale_set_breakpoint(target, breakpoint);
1161 breakpoint = breakpoint->next;
1162 }
1163 }
1164
1165 static int xscale_resume(struct target *target, int current,
1166 uint32_t address, int handle_breakpoints, int debug_execution)
1167 {
1168 struct xscale_common *xscale = target_to_xscale(target);
1169 struct arm *armv4_5 = &xscale->armv4_5_common;
1170 struct breakpoint *breakpoint = target->breakpoints;
1171 uint32_t current_pc;
1172 int retval;
1173 int i;
1174
1175 LOG_DEBUG("-");
1176
1177 if (target->state != TARGET_HALTED)
1178 {
1179 LOG_WARNING("target not halted");
1180 return ERROR_TARGET_NOT_HALTED;
1181 }
1182
1183 if (!debug_execution)
1184 {
1185 target_free_all_working_areas(target);
1186 }
1187
1188 /* update vector tables */
1189 if ((retval = xscale_update_vectors(target)) != ERROR_OK)
1190 return retval;
1191
1192 /* current = 1: continue on current pc, otherwise continue at <address> */
1193 if (!current)
1194 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1195
1196 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1197
1198 /* if we're at the reset vector, we have to simulate the branch */
1199 if (current_pc == 0x0)
1200 {
1201 arm_simulate_step(target, NULL);
1202 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1203 }
1204
1205 /* the front-end may request us not to handle breakpoints */
1206 if (handle_breakpoints)
1207 {
1208 breakpoint = breakpoint_find(target,
1209 buf_get_u32(armv4_5->pc->value, 0, 32));
1210 if (breakpoint != NULL)
1211 {
1212 uint32_t next_pc;
1213 int saved_trace_buffer_enabled;
1214
1215 /* there's a breakpoint at the current PC, we have to step over it */
1216 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1217 xscale_unset_breakpoint(target, breakpoint);
1218
1219 /* calculate PC of next instruction */
1220 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1221 {
1222 uint32_t current_opcode;
1223 target_read_u32(target, current_pc, &current_opcode);
1224 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1225 }
1226
1227 LOG_DEBUG("enable single-step");
1228 xscale_enable_single_step(target, next_pc);
1229
1230 /* restore banked registers */
1231 retval = xscale_restore_banked(target);
1232
1233 /* send resume request */
1234 xscale_send_u32(target, 0x30);
1235
1236 /* send CPSR */
1237 xscale_send_u32(target,
1238 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1239 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1240 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1241
1242 for (i = 7; i >= 0; i--)
1243 {
1244 /* send register */
1245 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1246 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1247 }
1248
1249 /* send PC */
1250 xscale_send_u32(target,
1251 buf_get_u32(armv4_5->pc->value, 0, 32));
1252 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1253 buf_get_u32(armv4_5->pc->value, 0, 32));
1254
1255 /* disable trace data collection in xscale_debug_entry() */
1256 saved_trace_buffer_enabled = xscale->trace.buffer_enabled;
1257 xscale->trace.buffer_enabled = 0;
1258
1259 /* wait for and process debug entry */
1260 xscale_debug_entry(target);
1261
1262 /* re-enable trace buffer, if enabled previously */
1263 xscale->trace.buffer_enabled = saved_trace_buffer_enabled;
1264
1265 LOG_DEBUG("disable single-step");
1266 xscale_disable_single_step(target);
1267
1268 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1269 xscale_set_breakpoint(target, breakpoint);
1270 }
1271 }
1272
1273 /* enable any pending breakpoints and watchpoints */
1274 xscale_enable_breakpoints(target);
1275 xscale_enable_watchpoints(target);
1276
1277 /* restore banked registers */
1278 retval = xscale_restore_banked(target);
1279
1280 /* send resume request (command 0x30 or 0x31)
1281 * clean the trace buffer if it is to be enabled (0x62) */
1282 if (xscale->trace.buffer_enabled)
1283 {
1284 xscale_send_u32(target, 0x62);
1285 xscale_send_u32(target, 0x31);
1286 }
1287 else
1288 xscale_send_u32(target, 0x30);
1289
1290 /* send CPSR */
1291 xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
1292 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1293 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1294
1295 for (i = 7; i >= 0; i--)
1296 {
1297 /* send register */
1298 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1299 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1300 }
1301
1302 /* send PC */
1303 xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32));
1304 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1305 buf_get_u32(armv4_5->pc->value, 0, 32));
1306
1307 target->debug_reason = DBG_REASON_NOTHALTED;
1308
1309 if (!debug_execution)
1310 {
1311 /* registers are now invalid */
1312 register_cache_invalidate(armv4_5->core_cache);
1313 target->state = TARGET_RUNNING;
1314 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1315 }
1316 else
1317 {
1318 target->state = TARGET_DEBUG_RUNNING;
1319 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1320 }
1321
1322 LOG_DEBUG("target resumed");
1323
1324 return ERROR_OK;
1325 }
1326
1327 static int xscale_step_inner(struct target *target, int current,
1328 uint32_t address, int handle_breakpoints)
1329 {
1330 struct xscale_common *xscale = target_to_xscale(target);
1331 struct arm *armv4_5 = &xscale->armv4_5_common;
1332 uint32_t next_pc;
1333 int retval;
1334 int i;
1335
1336 target->debug_reason = DBG_REASON_SINGLESTEP;
1337
1338 /* calculate PC of next instruction */
1339 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1340 {
1341 uint32_t current_opcode, current_pc;
1342 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1343
1344 target_read_u32(target, current_pc, &current_opcode);
1345 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1346 return retval;
1347 }
1348
1349 LOG_DEBUG("enable single-step");
1350 if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK)
1351 return retval;
1352
1353 /* restore banked registers */
1354 if ((retval = xscale_restore_banked(target)) != ERROR_OK)
1355 return retval;
1356
1357 /* send resume request (command 0x30 or 0x31)
1358 * clean the trace buffer if it is to be enabled (0x62) */
1359 if (xscale->trace.buffer_enabled)
1360 {
1361 if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK)
1362 return retval;
1363 if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK)
1364 return retval;
1365 }
1366 else
1367 if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK)
1368 return retval;
1369
1370 /* send CPSR */
1371 retval = xscale_send_u32(target,
1372 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1373 if (retval != ERROR_OK)
1374 return retval;
1375 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1376 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1377
1378 for (i = 7; i >= 0; i--)
1379 {
1380 /* send register */
1381 if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
1382 return retval;
1383 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1384 }
1385
1386 /* send PC */
1387 retval = xscale_send_u32(target,
1388 buf_get_u32(armv4_5->pc->value, 0, 32));
1389 if (retval != ERROR_OK)
1390 return retval;
1391 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1392 buf_get_u32(armv4_5->pc->value, 0, 32));
1393
1394 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1395
1396 /* registers are now invalid */
1397 register_cache_invalidate(armv4_5->core_cache);
1398
1399 /* wait for and process debug entry */
1400 if ((retval = xscale_debug_entry(target)) != ERROR_OK)
1401 return retval;
1402
1403 LOG_DEBUG("disable single-step");
1404 if ((retval = xscale_disable_single_step(target)) != ERROR_OK)
1405 return retval;
1406
1407 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1408
1409 return ERROR_OK;
1410 }
1411
1412 static int xscale_step(struct target *target, int current,
1413 uint32_t address, int handle_breakpoints)
1414 {
1415 struct arm *armv4_5 = target_to_arm(target);
1416 struct breakpoint *breakpoint = NULL;
1417
1418 uint32_t current_pc;
1419 int retval;
1420
1421 if (target->state != TARGET_HALTED)
1422 {
1423 LOG_WARNING("target not halted");
1424 return ERROR_TARGET_NOT_HALTED;
1425 }
1426
1427 /* current = 1: continue on current pc, otherwise continue at <address> */
1428 if (!current)
1429 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1430
1431 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1432
1433 /* if we're at the reset vector, we have to simulate the step */
1434 if (current_pc == 0x0)
1435 {
1436 if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
1437 return retval;
1438 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1439
1440 target->debug_reason = DBG_REASON_SINGLESTEP;
1441 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1442
1443 return ERROR_OK;
1444 }
1445
1446 /* the front-end may request us not to handle breakpoints */
1447 if (handle_breakpoints)
1448 breakpoint = breakpoint_find(target,
1449 buf_get_u32(armv4_5->pc->value, 0, 32));
1450 if (breakpoint != NULL) {
1451 retval = xscale_unset_breakpoint(target, breakpoint);
1452 if (retval != ERROR_OK)
1453 return retval;
1454 }
1455
1456 retval = xscale_step_inner(target, current, address, handle_breakpoints);
1457
1458 if (breakpoint)
1459 {
1460 xscale_set_breakpoint(target, breakpoint);
1461 }
1462
1463 LOG_DEBUG("target stepped");
1464
1465 return ERROR_OK;
1466
1467 }
1468
1469 static int xscale_assert_reset(struct target *target)
1470 {
1471 struct xscale_common *xscale = target_to_xscale(target);
1472
1473 LOG_DEBUG("target->state: %s",
1474 target_state_name(target));
1475
1476 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1477 * end up in T-L-R, which would reset JTAG
1478 */
1479 xscale_jtag_set_instr(target->tap,
1480 XSCALE_SELDCSR << xscale->xscale_variant,
1481 TAP_IDLE);
1482
1483 /* set Hold reset, Halt mode and Trap Reset */
1484 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1485 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1486 xscale_write_dcsr(target, 1, 0);
1487
1488 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1489 xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
1490 jtag_execute_queue();
1491
1492 /* assert reset */
1493 jtag_add_reset(0, 1);
1494
1495 /* sleep 1ms, to be sure we fulfill any requirements */
1496 jtag_add_sleep(1000);
1497 jtag_execute_queue();
1498
1499 target->state = TARGET_RESET;
1500
1501 if (target->reset_halt)
1502 {
1503 int retval;
1504 if ((retval = target_halt(target)) != ERROR_OK)
1505 return retval;
1506 }
1507
1508 return ERROR_OK;
1509 }
1510
1511 static int xscale_deassert_reset(struct target *target)
1512 {
1513 struct xscale_common *xscale = target_to_xscale(target);
1514 struct breakpoint *breakpoint = target->breakpoints;
1515
1516 LOG_DEBUG("-");
1517
1518 xscale->ibcr_available = 2;
1519 xscale->ibcr0_used = 0;
1520 xscale->ibcr1_used = 0;
1521
1522 xscale->dbr_available = 2;
1523 xscale->dbr0_used = 0;
1524 xscale->dbr1_used = 0;
1525
1526 /* mark all hardware breakpoints as unset */
1527 while (breakpoint)
1528 {
1529 if (breakpoint->type == BKPT_HARD)
1530 {
1531 breakpoint->set = 0;
1532 }
1533 breakpoint = breakpoint->next;
1534 }
1535
1536 register_cache_invalidate(xscale->armv4_5_common.core_cache);
1537
1538 /* FIXME mark hardware watchpoints got unset too. Also,
1539 * at least some of the XScale registers are invalid...
1540 */
1541
1542 /*
1543 * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
1544 * contents got invalidated. Safer to force that, so writing new
1545 * contents can't ever fail..
1546 */
1547 {
1548 uint32_t address;
1549 unsigned buf_cnt;
1550 const uint8_t *buffer = xscale_debug_handler;
1551 int retval;
1552
1553 /* release SRST */
1554 jtag_add_reset(0, 0);
1555
1556 /* wait 300ms; 150 and 100ms were not enough */
1557 jtag_add_sleep(300*1000);
1558
1559 jtag_add_runtest(2030, TAP_IDLE);
1560 jtag_execute_queue();
1561
1562 /* set Hold reset, Halt mode and Trap Reset */
1563 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1564 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1565 xscale_write_dcsr(target, 1, 0);
1566
1567 /* Load the debug handler into the mini-icache. Since
1568 * it's using halt mode (not monitor mode), it runs in
1569 * "Special Debug State" for access to registers, memory,
1570 * coprocessors, trace data, etc.
1571 */
1572 address = xscale->handler_address;
1573 for (unsigned binary_size = sizeof xscale_debug_handler - 1;
1574 binary_size > 0;
1575 binary_size -= buf_cnt, buffer += buf_cnt)
1576 {
1577 uint32_t cache_line[8];
1578 unsigned i;
1579
1580 buf_cnt = binary_size;
1581 if (buf_cnt > 32)
1582 buf_cnt = 32;
1583
1584 for (i = 0; i < buf_cnt; i += 4)
1585 {
1586 /* convert LE buffer to host-endian uint32_t */
1587 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1588 }
1589
1590 for (; i < 32; i += 4)
1591 {
1592 cache_line[i / 4] = 0xe1a08008;
1593 }
1594
1595 /* only load addresses other than the reset vectors */
1596 if ((address % 0x400) != 0x0)
1597 {
1598 retval = xscale_load_ic(target, address,
1599 cache_line);
1600 if (retval != ERROR_OK)
1601 return retval;
1602 }
1603
1604 address += buf_cnt;
1605 };
1606
1607 retval = xscale_load_ic(target, 0x0,
1608 xscale->low_vectors);
1609 if (retval != ERROR_OK)
1610 return retval;
1611 retval = xscale_load_ic(target, 0xffff0000,
1612 xscale->high_vectors);
1613 if (retval != ERROR_OK)
1614 return retval;
1615
1616 jtag_add_runtest(30, TAP_IDLE);
1617
1618 jtag_add_sleep(100000);
1619
1620 /* set Hold reset, Halt mode and Trap Reset */
1621 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1622 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1623 xscale_write_dcsr(target, 1, 0);
1624
1625 /* clear Hold reset to let the target run (should enter debug handler) */
1626 xscale_write_dcsr(target, 0, 1);
1627 target->state = TARGET_RUNNING;
1628
1629 if (!target->reset_halt)
1630 {
1631 jtag_add_sleep(10000);
1632
1633 /* we should have entered debug now */
1634 xscale_debug_entry(target);
1635 target->state = TARGET_HALTED;
1636
1637 /* resume the target */
1638 xscale_resume(target, 1, 0x0, 1, 0);
1639 }
1640 }
1641
1642 return ERROR_OK;
1643 }
1644
1645 static int xscale_read_core_reg(struct target *target, struct reg *r,
1646 int num, enum arm_mode mode)
1647 {
1648 /** \todo add debug handler support for core register reads */
1649 LOG_ERROR("not implemented");
1650 return ERROR_OK;
1651 }
1652
1653 static int xscale_write_core_reg(struct target *target, struct reg *r,
1654 int num, enum arm_mode mode, uint32_t value)
1655 {
1656 /** \todo add debug handler support for core register writes */
1657 LOG_ERROR("not implemented");
1658 return ERROR_OK;
1659 }
1660
1661 static int xscale_full_context(struct target *target)
1662 {
1663 struct arm *armv4_5 = target_to_arm(target);
1664
1665 uint32_t *buffer;
1666
1667 int i, j;
1668
1669 LOG_DEBUG("-");
1670
1671 if (target->state != TARGET_HALTED)
1672 {
1673 LOG_WARNING("target not halted");
1674 return ERROR_TARGET_NOT_HALTED;
1675 }
1676
1677 buffer = malloc(4 * 8);
1678
1679 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1680 * we can't enter User mode on an XScale (unpredictable),
1681 * but User shares registers with SYS
1682 */
1683 for (i = 1; i < 7; i++)
1684 {
1685 enum arm_mode mode = armv4_5_number_to_mode(i);
1686 bool valid = true;
1687 struct reg *r;
1688
1689 if (mode == ARM_MODE_USR)
1690 continue;
1691
1692 /* check if there are invalid registers in the current mode
1693 */
1694 for (j = 0; valid && j <= 16; j++)
1695 {
1696 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1697 mode, j).valid)
1698 valid = false;
1699 }
1700 if (valid)
1701 continue;
1702
1703 /* request banked registers */
1704 xscale_send_u32(target, 0x0);
1705
1706 /* send CPSR for desired bank mode */
1707 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1708
1709 /* get banked registers: r8 to r14; and SPSR
1710 * except in USR/SYS mode
1711 */
1712 if (mode != ARM_MODE_SYS) {
1713 /* SPSR */
1714 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1715 mode, 16);
1716
1717 xscale_receive(target, buffer, 8);
1718
1719 buf_set_u32(r->value, 0, 32, buffer[7]);
1720 r->dirty = false;
1721 r->valid = true;
1722 } else {
1723 xscale_receive(target, buffer, 7);
1724 }
1725
1726 /* move data from buffer to register cache */
1727 for (j = 8; j <= 14; j++)
1728 {
1729 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1730 mode, j);
1731
1732 buf_set_u32(r->value, 0, 32, buffer[j - 8]);
1733 r->dirty = false;
1734 r->valid = true;
1735 }
1736 }
1737
1738 free(buffer);
1739
1740 return ERROR_OK;
1741 }
1742
1743 static int xscale_restore_banked(struct target *target)
1744 {
1745 struct arm *armv4_5 = target_to_arm(target);
1746
1747 int i, j;
1748
1749 if (target->state != TARGET_HALTED)
1750 {
1751 LOG_WARNING("target not halted");
1752 return ERROR_TARGET_NOT_HALTED;
1753 }
1754
1755 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1756 * and check if any banked registers need to be written. Ignore
1757 * USR mode (number 0) in favor of SYS; we can't enter User mode on
1758 * an XScale (unpredictable), but they share all registers.
1759 */
1760 for (i = 1; i < 7; i++)
1761 {
1762 enum arm_mode mode = armv4_5_number_to_mode(i);
1763 struct reg *r;
1764
1765 if (mode == ARM_MODE_USR)
1766 continue;
1767
1768 /* check if there are dirty registers in this mode */
1769 for (j = 8; j <= 14; j++)
1770 {
1771 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1772 mode, j).dirty)
1773 goto dirty;
1774 }
1775
1776 /* if not USR/SYS, check if the SPSR needs to be written */
1777 if (mode != ARM_MODE_SYS)
1778 {
1779 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1780 mode, 16).dirty)
1781 goto dirty;
1782 }
1783
1784 /* there's nothing to flush for this mode */
1785 continue;
1786
1787 dirty:
1788 /* command 0x1: "send banked registers" */
1789 xscale_send_u32(target, 0x1);
1790
1791 /* send CPSR for desired mode */
1792 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1793
1794 /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
1795 * but this protocol doesn't understand that nuance.
1796 */
1797 for (j = 8; j <= 14; j++) {
1798 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1799 mode, j);
1800 xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1801 r->dirty = false;
1802 }
1803
1804 /* send spsr if not in USR/SYS mode */
1805 if (mode != ARM_MODE_SYS) {
1806 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1807 mode, 16);
1808 xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1809 r->dirty = false;
1810 }
1811 }
1812
1813 return ERROR_OK;
1814 }
1815
1816 static int xscale_read_memory(struct target *target, uint32_t address,
1817 uint32_t size, uint32_t count, uint8_t *buffer)
1818 {
1819 struct xscale_common *xscale = target_to_xscale(target);
1820 uint32_t *buf32;
1821 uint32_t i;
1822 int retval;
1823
1824 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1825
1826 if (target->state != TARGET_HALTED)
1827 {
1828 LOG_WARNING("target not halted");
1829 return ERROR_TARGET_NOT_HALTED;
1830 }
1831
1832 /* sanitize arguments */
1833 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1834 return ERROR_INVALID_ARGUMENTS;
1835
1836 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1837 return ERROR_TARGET_UNALIGNED_ACCESS;
1838
1839 /* send memory read request (command 0x1n, n: access size) */
1840 if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
1841 return retval;
1842
1843 /* send base address for read request */
1844 if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1845 return retval;
1846
1847 /* send number of requested data words */
1848 if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1849 return retval;
1850
1851 /* receive data from target (count times 32-bit words in host endianness) */
1852 buf32 = malloc(4 * count);
1853 if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK)
1854 return retval;
1855
1856 /* extract data from host-endian buffer into byte stream */
1857 for (i = 0; i < count; i++)
1858 {
1859 switch (size)
1860 {
1861 case 4:
1862 target_buffer_set_u32(target, buffer, buf32[i]);
1863 buffer += 4;
1864 break;
1865 case 2:
1866 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1867 buffer += 2;
1868 break;
1869 case 1:
1870 *buffer++ = buf32[i] & 0xff;
1871 break;
1872 default:
1873 LOG_ERROR("invalid read size");
1874 return ERROR_INVALID_ARGUMENTS;
1875 }
1876 }
1877
1878 free(buf32);
1879
1880 /* examine DCSR, to see if Sticky Abort (SA) got set */
1881 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1882 return retval;
1883 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1884 {
1885 /* clear SA bit */
1886 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1887 return retval;
1888
1889 return ERROR_TARGET_DATA_ABORT;
1890 }
1891
1892 return ERROR_OK;
1893 }
1894
1895 static int xscale_read_phys_memory(struct target *target, uint32_t address,
1896 uint32_t size, uint32_t count, uint8_t *buffer)
1897 {
1898 struct xscale_common *xscale = target_to_xscale(target);
1899
1900 /* with MMU inactive, there are only physical addresses */
1901 if (!xscale->armv4_5_mmu.mmu_enabled)
1902 return xscale_read_memory(target, address, size, count, buffer);
1903
1904 /** \todo: provide a non-stub implementation of this routine. */
1905 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1906 target_name(target), __func__);
1907 return ERROR_FAIL;
1908 }
1909
1910 static int xscale_write_memory(struct target *target, uint32_t address,
1911 uint32_t size, uint32_t count, uint8_t *buffer)
1912 {
1913 struct xscale_common *xscale = target_to_xscale(target);
1914 int retval;
1915
1916 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1917
1918 if (target->state != TARGET_HALTED)
1919 {
1920 LOG_WARNING("target not halted");
1921 return ERROR_TARGET_NOT_HALTED;
1922 }
1923
1924 /* sanitize arguments */
1925 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1926 return ERROR_INVALID_ARGUMENTS;
1927
1928 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1929 return ERROR_TARGET_UNALIGNED_ACCESS;
1930
1931 /* send memory write request (command 0x2n, n: access size) */
1932 if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
1933 return retval;
1934
1935 /* send base address for read request */
1936 if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1937 return retval;
1938
1939 /* send number of requested data words to be written*/
1940 if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1941 return retval;
1942
1943 /* extract data from host-endian buffer into byte stream */
1944 #if 0
1945 for (i = 0; i < count; i++)
1946 {
1947 switch (size)
1948 {
1949 case 4:
1950 value = target_buffer_get_u32(target, buffer);
1951 xscale_send_u32(target, value);
1952 buffer += 4;
1953 break;
1954 case 2:
1955 value = target_buffer_get_u16(target, buffer);
1956 xscale_send_u32(target, value);
1957 buffer += 2;
1958 break;
1959 case 1:
1960 value = *buffer;
1961 xscale_send_u32(target, value);
1962 buffer += 1;
1963 break;
1964 default:
1965 LOG_ERROR("should never get here");
1966 exit(-1);
1967 }
1968 }
1969 #endif
1970 if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK)
1971 return retval;
1972
1973 /* examine DCSR, to see if Sticky Abort (SA) got set */
1974 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1975 return retval;
1976 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1977 {
1978 /* clear SA bit */
1979 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1980 return retval;
1981
1982 return ERROR_TARGET_DATA_ABORT;
1983 }
1984
1985 return ERROR_OK;
1986 }
1987
1988 static int xscale_write_phys_memory(struct target *target, uint32_t address,
1989 uint32_t size, uint32_t count, uint8_t *buffer)
1990 {
1991 struct xscale_common *xscale = target_to_xscale(target);
1992
1993 /* with MMU inactive, there are only physical addresses */
1994 if (!xscale->armv4_5_mmu.mmu_enabled)
1995 return xscale_read_memory(target, address, size, count, buffer);
1996
1997 /** \todo: provide a non-stub implementation of this routine. */
1998 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1999 target_name(target), __func__);
2000 return ERROR_FAIL;
2001 }
2002
2003 static int xscale_bulk_write_memory(struct target *target, uint32_t address,
2004 uint32_t count, uint8_t *buffer)
2005 {
2006 return xscale_write_memory(target, address, 4, count, buffer);
2007 }
2008
2009 static int xscale_get_ttb(struct target *target, uint32_t *result)
2010 {
2011 struct xscale_common *xscale = target_to_xscale(target);
2012 uint32_t ttb;
2013 int retval;
2014
2015 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2016 if (retval != ERROR_OK)
2017 return retval;
2018 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2019
2020 *result = ttb;
2021
2022 return ERROR_OK;
2023 }
2024
2025 static int xscale_disable_mmu_caches(struct target *target, int mmu,
2026 int d_u_cache, int i_cache)
2027 {
2028 struct xscale_common *xscale = target_to_xscale(target);
2029 uint32_t cp15_control;
2030 int retval;
2031
2032 /* read cp15 control register */
2033 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2034 if (retval !=ERROR_OK)
2035 return retval;
2036 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2037
2038 if (mmu)
2039 cp15_control &= ~0x1U;
2040
2041 if (d_u_cache)
2042 {
2043 /* clean DCache */
2044 retval = xscale_send_u32(target, 0x50);
2045 if (retval !=ERROR_OK)
2046 return retval;
2047 retval = xscale_send_u32(target, xscale->cache_clean_address);
2048 if (retval !=ERROR_OK)
2049 return retval;
2050
2051 /* invalidate DCache */
2052 retval = xscale_send_u32(target, 0x51);
2053 if (retval !=ERROR_OK)
2054 return retval;
2055
2056 cp15_control &= ~0x4U;
2057 }
2058
2059 if (i_cache)
2060 {
2061 /* invalidate ICache */
2062 retval = xscale_send_u32(target, 0x52);
2063 if (retval !=ERROR_OK)
2064 return retval;
2065 cp15_control &= ~0x1000U;
2066 }
2067
2068 /* write new cp15 control register */
2069 retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2070 if (retval !=ERROR_OK)
2071 return retval;
2072
2073 /* execute cpwait to ensure outstanding operations complete */
2074 retval = xscale_send_u32(target, 0x53);
2075 return retval;
2076 }
2077
2078 static int xscale_enable_mmu_caches(struct target *target, int mmu,
2079 int d_u_cache, int i_cache)
2080 {
2081 struct xscale_common *xscale = target_to_xscale(target);
2082 uint32_t cp15_control;
2083 int retval;
2084
2085 /* read cp15 control register */
2086 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2087 if (retval !=ERROR_OK)
2088 return retval;
2089 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2090
2091 if (mmu)
2092 cp15_control |= 0x1U;
2093
2094 if (d_u_cache)
2095 cp15_control |= 0x4U;
2096
2097 if (i_cache)
2098 cp15_control |= 0x1000U;
2099
2100 /* write new cp15 control register */
2101 retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2102 if (retval !=ERROR_OK)
2103 return retval;
2104
2105 /* execute cpwait to ensure outstanding operations complete */
2106 retval = xscale_send_u32(target, 0x53);
2107 return retval;
2108 }
2109
2110 static int xscale_set_breakpoint(struct target *target,
2111 struct breakpoint *breakpoint)
2112 {
2113 int retval;
2114 struct xscale_common *xscale = target_to_xscale(target);
2115
2116 if (target->state != TARGET_HALTED)
2117 {
2118 LOG_WARNING("target not halted");
2119 return ERROR_TARGET_NOT_HALTED;
2120 }
2121
2122 if (breakpoint->set)
2123 {
2124 LOG_WARNING("breakpoint already set");
2125 return ERROR_OK;
2126 }
2127
2128 if (breakpoint->type == BKPT_HARD)
2129 {
2130 uint32_t value = breakpoint->address | 1;
2131 if (!xscale->ibcr0_used)
2132 {
2133 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2134 xscale->ibcr0_used = 1;
2135 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2136 }
2137 else if (!xscale->ibcr1_used)
2138 {
2139 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2140 xscale->ibcr1_used = 1;
2141 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2142 }
2143 else
2144 {
2145 LOG_ERROR("BUG: no hardware comparator available");
2146 return ERROR_OK;
2147 }
2148 }
2149 else if (breakpoint->type == BKPT_SOFT)
2150 {
2151 if (breakpoint->length == 4)
2152 {
2153 /* keep the original instruction in target endianness */
2154 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2155 {
2156 return retval;
2157 }
2158 /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2159 if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
2160 {
2161 return retval;
2162 }
2163 }
2164 else
2165 {
2166 /* keep the original instruction in target endianness */
2167 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2168 {
2169 return retval;
2170 }
2171 /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2172 if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
2173 {
2174 return retval;
2175 }
2176 }
2177 breakpoint->set = 1;
2178
2179 xscale_send_u32(target, 0x50); /* clean dcache */
2180 xscale_send_u32(target, xscale->cache_clean_address);
2181 xscale_send_u32(target, 0x51); /* invalidate dcache */
2182 xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
2183 }
2184
2185 return ERROR_OK;
2186 }
2187
2188 static int xscale_add_breakpoint(struct target *target,
2189 struct breakpoint *breakpoint)
2190 {
2191 struct xscale_common *xscale = target_to_xscale(target);
2192
2193 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2194 {
2195 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2196 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2197 }
2198
2199 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2200 {
2201 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2202 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2203 }
2204
2205 if (breakpoint->type == BKPT_HARD)
2206 {
2207 xscale->ibcr_available--;
2208 }
2209
2210 return ERROR_OK;
2211 }
2212
2213 static int xscale_unset_breakpoint(struct target *target,
2214 struct breakpoint *breakpoint)
2215 {
2216 int retval;
2217 struct xscale_common *xscale = target_to_xscale(target);
2218
2219 if (target->state != TARGET_HALTED)
2220 {
2221 LOG_WARNING("target not halted");
2222 return ERROR_TARGET_NOT_HALTED;
2223 }
2224
2225 if (!breakpoint->set)
2226 {
2227 LOG_WARNING("breakpoint not set");
2228 return ERROR_OK;
2229 }
2230
2231 if (breakpoint->type == BKPT_HARD)
2232 {
2233 if (breakpoint->set == 1)
2234 {
2235 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2236 xscale->ibcr0_used = 0;
2237 }
2238 else if (breakpoint->set == 2)
2239 {
2240 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2241 xscale->ibcr1_used = 0;
2242 }
2243 breakpoint->set = 0;
2244 }
2245 else
2246 {
2247 /* restore original instruction (kept in target endianness) */
2248 if (breakpoint->length == 4)
2249 {
2250 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2251 {
2252 return retval;
2253 }
2254 }
2255 else
2256 {
2257 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2258 {
2259 return retval;
2260 }
2261 }
2262 breakpoint->set = 0;
2263
2264 xscale_send_u32(target, 0x50); /* clean dcache */
2265 xscale_send_u32(target, xscale->cache_clean_address);
2266 xscale_send_u32(target, 0x51); /* invalidate dcache */
2267 xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
2268 }
2269
2270 return ERROR_OK;
2271 }
2272
2273 static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2274 {
2275 struct xscale_common *xscale = target_to_xscale(target);
2276
2277 if (target->state != TARGET_HALTED)
2278 {
2279 LOG_WARNING("target not halted");
2280 return ERROR_TARGET_NOT_HALTED;
2281 }
2282
2283 if (breakpoint->set)
2284 {
2285 xscale_unset_breakpoint(target, breakpoint);
2286 }
2287
2288 if (breakpoint->type == BKPT_HARD)
2289 xscale->ibcr_available++;
2290
2291 return ERROR_OK;
2292 }
2293
2294 static int xscale_set_watchpoint(struct target *target,
2295 struct watchpoint *watchpoint)
2296 {
2297 struct xscale_common *xscale = target_to_xscale(target);
2298 uint32_t enable = 0;
2299 struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2300 uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2301
2302 if (target->state != TARGET_HALTED)
2303 {
2304 LOG_WARNING("target not halted");
2305 return ERROR_TARGET_NOT_HALTED;
2306 }
2307
2308 switch (watchpoint->rw)
2309 {
2310 case WPT_READ:
2311 enable = 0x3;
2312 break;
2313 case WPT_ACCESS:
2314 enable = 0x2;
2315 break;
2316 case WPT_WRITE:
2317 enable = 0x1;
2318 break;
2319 default:
2320 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2321 }
2322
2323 /* For watchpoint across more than one word, both DBR registers must
2324 be enlisted, with the second used as a mask. */
2325 if (watchpoint->length > 4)
2326 {
2327 if (xscale->dbr0_used || xscale->dbr1_used)
2328 {
2329 LOG_ERROR("BUG: sufficient hardware comparators unavailable");
2330 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2331 }
2332
2333 /* Write mask value to DBR1, based on the length argument.
2334 * Address bits ignored by the comparator are those set in mask. */
2335 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
2336 watchpoint->length - 1);
2337 xscale->dbr1_used = 1;
2338 enable |= 0x100; /* DBCON[M] */
2339 }
2340
2341 if (!xscale->dbr0_used)
2342 {
2343 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2344 dbcon_value |= enable;
2345 xscale_set_reg_u32(dbcon, dbcon_value);
2346 watchpoint->set = 1;
2347 xscale->dbr0_used = 1;
2348 }
2349 else if (!xscale->dbr1_used)
2350 {
2351 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2352 dbcon_value |= enable << 2;
2353 xscale_set_reg_u32(dbcon, dbcon_value);
2354 watchpoint->set = 2;
2355 xscale->dbr1_used = 1;
2356 }
2357 else
2358 {
2359 LOG_ERROR("BUG: no hardware comparator available");
2360 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2361 }
2362
2363 return ERROR_OK;
2364 }
2365
2366 static int xscale_add_watchpoint(struct target *target,
2367 struct watchpoint *watchpoint)
2368 {
2369 struct xscale_common *xscale = target_to_xscale(target);
2370
2371 if (xscale->dbr_available < 1)
2372 {
2373 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2374 }
2375
2376 if (watchpoint->value)
2377 LOG_WARNING("xscale does not support value, mask arguments; ignoring");
2378
2379 /* check that length is a power of two */
2380 for (uint32_t len = watchpoint->length; len != 1; len /= 2)
2381 {
2382 if (len % 2)
2383 {
2384 LOG_ERROR("xscale requires that watchpoint length is a power of two");
2385 return ERROR_COMMAND_ARGUMENT_INVALID;
2386 }
2387 }
2388
2389 if (watchpoint->length == 4) /* single word watchpoint */
2390 {
2391 xscale->dbr_available--; /* one DBR reg used */
2392 return ERROR_OK;
2393 }
2394
2395 /* watchpoints across multiple words require both DBR registers */
2396 if (xscale->dbr_available < 2)
2397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2398
2399 xscale->dbr_available = 0;
2400 return ERROR_OK;
2401 }
2402
2403 static int xscale_unset_watchpoint(struct target *target,
2404 struct watchpoint *watchpoint)
2405 {
2406 struct xscale_common *xscale = target_to_xscale(target);
2407 struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2408 uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2409
2410 if (target->state != TARGET_HALTED)
2411 {
2412 LOG_WARNING("target not halted");
2413 return ERROR_TARGET_NOT_HALTED;
2414 }
2415
2416 if (!watchpoint->set)
2417 {
2418 LOG_WARNING("breakpoint not set");
2419 return ERROR_OK;
2420 }
2421
2422 if (watchpoint->set == 1)
2423 {
2424 if (watchpoint->length > 4)
2425 {
2426 dbcon_value &= ~0x103; /* clear DBCON[M] as well */
2427 xscale->dbr1_used = 0; /* DBR1 was used for mask */
2428 }
2429 else
2430 dbcon_value &= ~0x3;
2431
2432 xscale_set_reg_u32(dbcon, dbcon_value);
2433 xscale->dbr0_used = 0;
2434 }
2435 else if (watchpoint->set == 2)
2436 {
2437 dbcon_value &= ~0xc;
2438 xscale_set_reg_u32(dbcon, dbcon_value);
2439 xscale->dbr1_used = 0;
2440 }
2441 watchpoint->set = 0;
2442
2443 return ERROR_OK;
2444 }
2445
2446 static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
2447 {
2448 struct xscale_common *xscale = target_to_xscale(target);
2449
2450 if (target->state != TARGET_HALTED)
2451 {
2452 LOG_WARNING("target not halted");
2453 return ERROR_TARGET_NOT_HALTED;
2454 }
2455
2456 if (watchpoint->set)
2457 {
2458 xscale_unset_watchpoint(target, watchpoint);
2459 }
2460
2461 if (watchpoint->length > 4)
2462 xscale->dbr_available++; /* both DBR regs now available */
2463
2464 xscale->dbr_available++;
2465
2466 return ERROR_OK;
2467 }
2468
2469 static int xscale_get_reg(struct reg *reg)
2470 {
2471 struct xscale_reg *arch_info = reg->arch_info;
2472 struct target *target = arch_info->target;
2473 struct xscale_common *xscale = target_to_xscale(target);
2474
2475 /* DCSR, TX and RX are accessible via JTAG */
2476 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2477 {
2478 return xscale_read_dcsr(arch_info->target);
2479 }
2480 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2481 {
2482 /* 1 = consume register content */
2483 return xscale_read_tx(arch_info->target, 1);
2484 }
2485 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2486 {
2487 /* can't read from RX register (host -> debug handler) */
2488 return ERROR_OK;
2489 }
2490 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2491 {
2492 /* can't (explicitly) read from TXRXCTRL register */
2493 return ERROR_OK;
2494 }
2495 else /* Other DBG registers have to be transfered by the debug handler */
2496 {
2497 /* send CP read request (command 0x40) */
2498 xscale_send_u32(target, 0x40);
2499
2500 /* send CP register number */
2501 xscale_send_u32(target, arch_info->dbg_handler_number);
2502
2503 /* read register value */
2504 xscale_read_tx(target, 1);
2505 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2506
2507 reg->dirty = 0;
2508 reg->valid = 1;
2509 }
2510
2511 return ERROR_OK;
2512 }
2513
2514 static int xscale_set_reg(struct reg *reg, uint8_t* buf)
2515 {
2516 struct xscale_reg *arch_info = reg->arch_info;
2517 struct target *target = arch_info->target;
2518 struct xscale_common *xscale = target_to_xscale(target);
2519 uint32_t value = buf_get_u32(buf, 0, 32);
2520
2521 /* DCSR, TX and RX are accessible via JTAG */
2522 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2523 {
2524 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2525 return xscale_write_dcsr(arch_info->target, -1, -1);
2526 }
2527 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2528 {
2529 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2530 return xscale_write_rx(arch_info->target);
2531 }
2532 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2533 {
2534 /* can't write to TX register (debug-handler -> host) */
2535 return ERROR_OK;
2536 }
2537 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2538 {
2539 /* can't (explicitly) write to TXRXCTRL register */
2540 return ERROR_OK;
2541 }
2542 else /* Other DBG registers have to be transfered by the debug handler */
2543 {
2544 /* send CP write request (command 0x41) */
2545 xscale_send_u32(target, 0x41);
2546
2547 /* send CP register number */
2548 xscale_send_u32(target, arch_info->dbg_handler_number);
2549
2550 /* send CP register value */
2551 xscale_send_u32(target, value);
2552 buf_set_u32(reg->value, 0, 32, value);
2553 }
2554
2555 return ERROR_OK;
2556 }
2557
2558 static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
2559 {
2560 struct xscale_common *xscale = target_to_xscale(target);
2561 struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2562 struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
2563
2564 /* send CP write request (command 0x41) */
2565 xscale_send_u32(target, 0x41);
2566
2567 /* send CP register number */
2568 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2569
2570 /* send CP register value */
2571 xscale_send_u32(target, value);
2572 buf_set_u32(dcsr->value, 0, 32, value);
2573
2574 return ERROR_OK;
2575 }
2576
2577 static int xscale_read_trace(struct target *target)
2578 {
2579 struct xscale_common *xscale = target_to_xscale(target);
2580 struct arm *armv4_5 = &xscale->armv4_5_common;
2581 struct xscale_trace_data **trace_data_p;
2582
2583 /* 258 words from debug handler
2584 * 256 trace buffer entries
2585 * 2 checkpoint addresses
2586 */
2587 uint32_t trace_buffer[258];
2588 int is_address[256];
2589 int i, j;
2590 unsigned int num_checkpoints = 0;
2591
2592 if (target->state != TARGET_HALTED)
2593 {
2594 LOG_WARNING("target must be stopped to read trace data");
2595 return ERROR_TARGET_NOT_HALTED;
2596 }
2597
2598 /* send read trace buffer command (command 0x61) */
2599 xscale_send_u32(target, 0x61);
2600
2601 /* receive trace buffer content */
2602 xscale_receive(target, trace_buffer, 258);
2603
2604 /* parse buffer backwards to identify address entries */
2605 for (i = 255; i >= 0; i--)
2606 {
2607 /* also count number of checkpointed entries */
2608 if ((trace_buffer[i] & 0xe0) == 0xc0)
2609 num_checkpoints++;
2610
2611 is_address[i] = 0;
2612 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2613 ((trace_buffer[i] & 0xf0) == 0xd0))
2614 {
2615 if (i > 0)
2616 is_address[--i] = 1;
2617 if (i > 0)
2618 is_address[--i] = 1;
2619 if (i > 0)
2620 is_address[--i] = 1;
2621 if (i > 0)
2622 is_address[--i] = 1;
2623 }
2624 }
2625
2626
2627 /* search first non-zero entry that is not part of an address */
2628 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2629 ;
2630
2631 if (j == 256)
2632 {
2633 LOG_DEBUG("no trace data collected");
2634 return ERROR_XSCALE_NO_TRACE_DATA;
2635 }
2636
2637 /* account for possible partial address at buffer start (wrap mode only) */
2638 if (is_address[0])
2639 { /* first entry is address; complete set of 4? */
2640 i = 1;
2641 while (i < 4)
2642 if (!is_address[i++])
2643 break;
2644 if (i < 4)
2645 j += i; /* partial address; can't use it */
2646 }
2647
2648 /* if first valid entry is indirect branch, can't use that either (no address) */
2649 if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
2650 j++;
2651
2652 /* walk linked list to terminating entry */
2653 for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2654 ;
2655
2656 *trace_data_p = malloc(sizeof(struct xscale_trace_data));
2657 (*trace_data_p)->next = NULL;
2658 (*trace_data_p)->chkpt0 = trace_buffer[256];
2659 (*trace_data_p)->chkpt1 = trace_buffer[257];
2660 (*trace_data_p)->last_instruction =
2661 buf_get_u32(armv4_5->pc->value, 0, 32);
2662 (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
2663 (*trace_data_p)->depth = 256 - j;
2664 (*trace_data_p)->num_checkpoints = num_checkpoints;
2665
2666 for (i = j; i < 256; i++)
2667 {
2668 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2669 if (is_address[i])
2670 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2671 else
2672 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2673 }
2674
2675 return ERROR_OK;
2676 }
2677
2678 static int xscale_read_instruction(struct target *target, uint32_t pc,
2679 struct arm_instruction *instruction)
2680 {
2681 struct xscale_common *const xscale = target_to_xscale(target);
2682 int i;
2683 int section = -1;
2684 size_t size_read;
2685 uint32_t opcode;
2686 int retval;
2687
2688 if (!xscale->trace.image)
2689 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2690
2691 /* search for the section the current instruction belongs to */
2692 for (i = 0; i < xscale->trace.image->num_sections; i++)
2693 {
2694 if ((xscale->trace.image->sections[i].base_address <= pc) &&
2695 (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > pc))
2696 {
2697 section = i;
2698 break;
2699 }
2700 }
2701
2702 if (section == -1)
2703 {
2704 /* current instruction couldn't be found in the image */
2705 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2706 }
2707
2708 if (xscale->trace.core_state == ARM_STATE_ARM)
2709 {
2710 uint8_t buf[4];
2711 if ((retval = image_read_section(xscale->trace.image, section,
2712 pc - xscale->trace.image->sections[section].base_address,
2713 4, buf, &size_read)) != ERROR_OK)
2714 {
2715 LOG_ERROR("error while reading instruction: %i", retval);
2716 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2717 }
2718 opcode = target_buffer_get_u32(target, buf);
2719 arm_evaluate_opcode(opcode, pc, instruction);
2720 }
2721 else if (xscale->trace.core_state == ARM_STATE_THUMB)
2722 {
2723 uint8_t buf[2];
2724 if ((retval = image_read_section(xscale->trace.image, section,
2725 pc - xscale->trace.image->sections[section].base_address,
2726 2, buf, &size_read)) != ERROR_OK)
2727 {
2728 LOG_ERROR("error while reading instruction: %i", retval);
2729 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2730 }
2731 opcode = target_buffer_get_u16(target, buf);
2732 thumb_evaluate_opcode(opcode, pc, instruction);
2733 }
2734 else
2735 {
2736 LOG_ERROR("BUG: unknown core state encountered");
2737 exit(-1);
2738 }
2739
2740 return ERROR_OK;
2741 }
2742
2743 /* Extract address encoded into trace data.
2744 * Write result to address referenced by argument 'target', or 0 if incomplete. */
2745 static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
2746 int i, uint32_t *target)
2747 {
2748 /* if there are less than four entries prior to the indirect branch message
2749 * we can't extract the address */
2750 if (i < 4)
2751 *target = 0;
2752 else
2753 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2754 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2755 }
2756
2757 static inline void xscale_display_instruction(struct target *target, uint32_t pc,
2758 struct arm_instruction *instruction,
2759 struct command_context *cmd_ctx)
2760 {
2761 int retval = xscale_read_instruction(target, pc, instruction);
2762 if (retval == ERROR_OK)
2763 command_print(cmd_ctx, "%s", instruction->text);
2764 else
2765 command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc);
2766 }
2767
2768 static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
2769 {
2770 struct xscale_common *xscale = target_to_xscale(target);
2771 struct xscale_trace_data *trace_data = xscale->trace.data;
2772 int i, retval;
2773 uint32_t breakpoint_pc;
2774 struct arm_instruction instruction;
2775 uint32_t current_pc = 0; /* initialized when address determined */
2776
2777 if (!xscale->trace.image)
2778 LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
2779
2780 /* loop for each trace buffer that was loaded from target */
2781 while (trace_data)
2782 {
2783 int chkpt = 0; /* incremented as checkpointed entries found */
2784 int j;
2785
2786 /* FIXME: set this to correct mode when trace buffer is first enabled */
2787 xscale->trace.core_state = ARM_STATE_ARM;
2788
2789 /* loop for each entry in this trace buffer */
2790 for (i = 0; i < trace_data->depth; i++)
2791 {
2792 int exception = 0;
2793 uint32_t chkpt_reg = 0x0;
2794 uint32_t branch_target = 0;
2795 int count;
2796
2797 /* trace entry type is upper nybble of 'message byte' */
2798 int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4;
2799
2800 /* Target addresses of indirect branches are written into buffer
2801 * before the message byte representing the branch. Skip past it */
2802 if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2803 continue;
2804
2805 switch (trace_msg_type)
2806 {
2807 case 0: /* Exceptions */
2808 case 1:
2809 case 2:
2810 case 3:
2811 case 4:
2812 case 5:
2813 case 6:
2814 case 7:
2815 exception = (trace_data->entries[i].data & 0x70) >> 4;
2816
2817 /* FIXME: vector table may be at ffff0000 */
2818 branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
2819 break;
2820
2821 case 8: /* Direct Branch */
2822 break;
2823
2824 case 9: /* Indirect Branch */
2825 xscale_branch_address(trace_data, i, &branch_target);
2826 break;
2827
2828 case 13: /* Checkpointed Indirect Branch */
2829 xscale_branch_address(trace_data, i, &branch_target);
2830 if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2831 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */
2832 else
2833 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */
2834
2835 chkpt++;
2836 break;
2837
2838 case 12: /* Checkpointed Direct Branch */
2839 if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2840 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */
2841 else
2842 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */
2843
2844 /* if no current_pc, checkpoint will be starting point */
2845 if (current_pc == 0)
2846 branch_target = chkpt_reg;
2847
2848 chkpt++;
2849 break;
2850
2851 case 15: /* Roll-over */
2852 break;
2853
2854 default: /* Reserved */
2855 LOG_WARNING("trace is suspect: invalid trace message byte");
2856 continue;
2857
2858 }
2859
2860 /* If we don't have the current_pc yet, but we did get the branch target
2861 * (either from the trace buffer on indirect branch, or from a checkpoint reg),
2862 * then we can start displaying instructions at the next iteration, with
2863 * branch_target as the starting point.
2864 */
2865 if (current_pc == 0)
2866 {
2867 current_pc = branch_target; /* remains 0 unless branch_target obtained */
2868 continue;
2869 }
2870
2871 /* We have current_pc. Read and display the instructions from the image.
2872 * First, display count instructions (lower nybble of message byte). */
2873 count = trace_data->entries[i].data & 0x0f;
2874 for (j = 0; j < count; j++)
2875 {
2876 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2877 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2878 }
2879
2880 /* An additional instruction is implicitly added to count for
2881 * rollover and some exceptions: undef, swi, prefetch abort. */
2882 if ((trace_msg_type == 15) || (exception > 0 && exception < 4))
2883 {
2884 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2885 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2886 }
2887
2888 if (trace_msg_type == 15) /* rollover */
2889 continue;
2890
2891 if (exception)
2892 {
2893 command_print(cmd_ctx, "--- exception %i ---", exception);
2894 continue;
2895 }
2896
2897 /* not exception or rollover; next instruction is a branch and is
2898 * not included in the count */
2899 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2900
2901 /* for direct branches, extract branch destination from instruction */
2902 if ((trace_msg_type == 8) || (trace_msg_type == 12))
2903 {
2904 retval = xscale_read_instruction(target, current_pc, &instruction);
2905 if (retval == ERROR_OK)
2906 current_pc = instruction.info.b_bl_bx_blx.target_address;
2907 else
2908 current_pc = 0; /* branch destination unknown */
2909
2910 /* direct branch w/ checkpoint; can also get from checkpoint reg */
2911 if (trace_msg_type == 12)
2912 {
2913 if (current_pc == 0)
2914 current_pc = chkpt_reg;
2915 else if (current_pc != chkpt_reg) /* sanity check */
2916 LOG_WARNING("trace is suspect: checkpoint register "
2917 "inconsistent with adddress from image");
2918 }
2919
2920 if (current_pc == 0)
2921 command_print(cmd_ctx, "address unknown");
2922
2923 continue;
2924 }
2925
2926 /* indirect branch; the branch destination was read from trace buffer */
2927 if ((trace_msg_type == 9) || (trace_msg_type == 13))
2928 {
2929 current_pc = branch_target;
2930
2931 /* sanity check (checkpoint reg is redundant) */
2932 if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
2933 LOG_WARNING("trace is suspect: checkpoint register "
2934 "inconsistent with address from trace buffer");
2935 }
2936
2937 } /* END: for (i = 0; i < trace_data->depth; i++) */
2938
2939 breakpoint_pc = trace_data->last_instruction; /* used below */
2940 trace_data = trace_data->next;
2941
2942 } /* END: while (trace_data) */
2943
2944 /* Finally... display all instructions up to the value of the pc when the
2945 * debug break occurred (saved when trace data was collected from target).
2946 * This is necessary because the trace only records execution branches and 16
2947 * consecutive instructions (rollovers), so last few typically missed.
2948 */
2949 if (current_pc == 0)
2950 return ERROR_OK; /* current_pc was never found */
2951
2952 /* how many instructions remaining? */
2953 int gap_count = (breakpoint_pc - current_pc) /
2954 (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
2955
2956 /* should never be negative or over 16, but verify */
2957 if (gap_count < 0 || gap_count > 16)
2958 {
2959 LOG_WARNING("trace is suspect: excessive gap at end of trace");
2960 return ERROR_OK; /* bail; large number or negative value no good */
2961 }
2962
2963 /* display remaining instructions */
2964 for (i = 0; i < gap_count; i++)
2965 {
2966 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2967 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2968 }
2969
2970 return ERROR_OK;
2971 }
2972
2973 static const struct reg_arch_type xscale_reg_type = {
2974 .get = xscale_get_reg,
2975 .set = xscale_set_reg,
2976 };
2977
2978 static void xscale_build_reg_cache(struct target *target)
2979 {
2980 struct xscale_common *xscale = target_to_xscale(target);
2981 struct arm *armv4_5 = &xscale->armv4_5_common;
2982 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
2983 struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
2984 int i;
2985 int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
2986
2987 (*cache_p) = arm_build_reg_cache(target, armv4_5);
2988
2989 (*cache_p)->next = malloc(sizeof(struct reg_cache));
2990 cache_p = &(*cache_p)->next;
2991
2992 /* fill in values for the xscale reg cache */
2993 (*cache_p)->name = "XScale registers";
2994 (*cache_p)->next = NULL;
2995 (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
2996 (*cache_p)->num_regs = num_regs;
2997
2998 for (i = 0; i < num_regs; i++)
2999 {
3000 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
3001 (*cache_p)->reg_list[i].value = calloc(4, 1);
3002 (*cache_p)->reg_list[i].dirty = 0;
3003 (*cache_p)->reg_list[i].valid = 0;
3004 (*cache_p)->reg_list[i].size = 32;
3005 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
3006 (*cache_p)->reg_list[i].type = &xscale_reg_type;
3007 arch_info[i] = xscale_reg_arch_info[i];
3008 arch_info[i].target = target;
3009 }
3010
3011 xscale->reg_cache = (*cache_p);
3012 }
3013
3014 static int xscale_init_target(struct command_context *cmd_ctx,
3015 struct target *target)
3016 {
3017 xscale_build_reg_cache(target);
3018 return ERROR_OK;
3019 }
3020
3021 static int xscale_init_arch_info(struct target *target,
3022 struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
3023 {
3024 struct arm *armv4_5;
3025 uint32_t high_reset_branch, low_reset_branch;
3026 int i;
3027
3028 armv4_5 = &xscale->armv4_5_common;
3029
3030 /* store architecture specfic data */
3031 xscale->common_magic = XSCALE_COMMON_MAGIC;
3032
3033 /* we don't really *need* a variant param ... */
3034 if (variant) {
3035 int ir_length = 0;
3036
3037 if (strcmp(variant, "pxa250") == 0
3038 || strcmp(variant, "pxa255") == 0
3039 || strcmp(variant, "pxa26x") == 0)
3040 ir_length = 5;
3041 else if (strcmp(variant, "pxa27x") == 0
3042 || strcmp(variant, "ixp42x") == 0
3043 || strcmp(variant, "ixp45x") == 0
3044 || strcmp(variant, "ixp46x") == 0)
3045 ir_length = 7;
3046 else if (strcmp(variant, "pxa3xx") == 0)
3047 ir_length = 11;
3048 else
3049 LOG_WARNING("%s: unrecognized variant %s",
3050 tap->dotted_name, variant);
3051
3052 if (ir_length && ir_length != tap->ir_length) {
3053 LOG_WARNING("%s: IR length for %s is %d; fixing",
3054 tap->dotted_name, variant, ir_length);
3055 tap->ir_length = ir_length;
3056 }
3057 }
3058
3059 /* PXA3xx shifts the JTAG instructions */
3060 if (tap->ir_length == 11)
3061 xscale->xscale_variant = XSCALE_PXA3XX;
3062 else
3063 xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
3064
3065 /* the debug handler isn't installed (and thus not running) at this time */
3066 xscale->handler_address = 0xfe000800;
3067
3068 /* clear the vectors we keep locally for reference */
3069 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
3070 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
3071
3072 /* no user-specified vectors have been configured yet */
3073 xscale->static_low_vectors_set = 0x0;
3074 xscale->static_high_vectors_set = 0x0;
3075
3076 /* calculate branches to debug handler */
3077 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
3078 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
3079
3080 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
3081 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
3082
3083 for (i = 1; i <= 7; i++)
3084 {
3085 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3086 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3087 }
3088
3089 /* 64kB aligned region used for DCache cleaning */
3090 xscale->cache_clean_address = 0xfffe0000;
3091
3092 xscale->hold_rst = 0;
3093 xscale->external_debug_break = 0;
3094
3095 xscale->ibcr_available = 2;
3096 xscale->ibcr0_used = 0;
3097 xscale->ibcr1_used = 0;
3098
3099 xscale->dbr_available = 2;
3100 xscale->dbr0_used = 0;
3101 xscale->dbr1_used = 0;
3102
3103 LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
3104 target_name(target));
3105
3106 xscale->arm_bkpt = ARMV5_BKPT(0x0);
3107 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
3108
3109 xscale->vector_catch = 0x1;
3110
3111 xscale->trace.capture_status = TRACE_IDLE;
3112 xscale->trace.data = NULL;
3113 xscale->trace.image = NULL;
3114 xscale->trace.buffer_enabled = 0;
3115 xscale->trace.buffer_fill = 0;
3116
3117 /* prepare ARMv4/5 specific information */
3118 armv4_5->arch_info = xscale;
3119 armv4_5->read_core_reg = xscale_read_core_reg;
3120 armv4_5->write_core_reg = xscale_write_core_reg;
3121 armv4_5->full_context = xscale_full_context;
3122
3123 arm_init_arch_info(target, armv4_5);
3124
3125 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3126 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3127 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3128 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3129 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3130 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3131 xscale->armv4_5_mmu.has_tiny_pages = 1;
3132 xscale->armv4_5_mmu.mmu_enabled = 0;
3133
3134 return ERROR_OK;
3135 }
3136
3137 static int xscale_target_create(struct target *target, Jim_Interp *interp)
3138 {
3139 struct xscale_common *xscale;
3140
3141 if (sizeof xscale_debug_handler - 1 > 0x800) {
3142 LOG_ERROR("debug_handler.bin: larger than 2kb");
3143 return ERROR_FAIL;
3144 }
3145
3146 xscale = calloc(1, sizeof(*xscale));
3147 if (!xscale)
3148 return ERROR_FAIL;
3149
3150 return xscale_init_arch_info(target, xscale, target->tap,
3151 target->variant);
3152 }
3153
3154 COMMAND_HANDLER(xscale_handle_debug_handler_command)
3155 {
3156 struct target *target = NULL;
3157 struct xscale_common *xscale;
3158 int retval;
3159 uint32_t handler_address;
3160
3161 if (CMD_ARGC < 2)
3162 {
3163 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3164 return ERROR_OK;
3165 }
3166
3167 if ((target = get_target(CMD_ARGV[0])) == NULL)
3168 {
3169 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3170 return ERROR_FAIL;
3171 }
3172
3173 xscale = target_to_xscale(target);
3174 retval = xscale_verify_pointer(CMD_CTX, xscale);
3175 if (retval != ERROR_OK)
3176 return retval;
3177
3178 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
3179
3180 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3181 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3182 {
3183 xscale->handler_address = handler_address;
3184 }
3185 else
3186 {
3187 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3188 return ERROR_FAIL;
3189 }
3190
3191 return ERROR_OK;
3192 }
3193
3194 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
3195 {
3196 struct target *target = NULL;
3197 struct xscale_common *xscale;
3198 int retval;
3199 uint32_t cache_clean_address;
3200
3201 if (CMD_ARGC < 2)
3202 {
3203 return ERROR_COMMAND_SYNTAX_ERROR;
3204 }
3205
3206 target = get_target(CMD_ARGV[0]);
3207 if (target == NULL)
3208 {
3209 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3210 return ERROR_FAIL;
3211 }
3212 xscale = target_to_xscale(target);
3213 retval = xscale_verify_pointer(CMD_CTX, xscale);
3214 if (retval != ERROR_OK)
3215 return retval;
3216
3217 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
3218
3219 if (cache_clean_address & 0xffff)
3220 {
3221 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3222 }
3223 else
3224 {
3225 xscale->cache_clean_address = cache_clean_address;
3226 }
3227
3228 return ERROR_OK;
3229 }
3230
3231 COMMAND_HANDLER(xscale_handle_cache_info_command)
3232 {
3233 struct target *target = get_current_target(CMD_CTX);
3234 struct xscale_common *xscale = target_to_xscale(target);
3235 int retval;
3236
3237 retval = xscale_verify_pointer(CMD_CTX, xscale);
3238 if (retval != ERROR_OK)
3239 return retval;
3240
3241 return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
3242 }
3243
3244 static int xscale_virt2phys(struct target *target,
3245 uint32_t virtual, uint32_t *physical)
3246 {
3247 struct xscale_common *xscale = target_to_xscale(target);
3248 uint32_t cb;
3249
3250 if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
3251 LOG_ERROR(xscale_not);
3252 return ERROR_TARGET_INVALID;
3253 }
3254
3255 uint32_t ret;
3256 int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
3257 virtual, &cb, &ret);
3258 if (retval != ERROR_OK)
3259 return retval;
3260 *physical = ret;
3261 return ERROR_OK;
3262 }
3263
3264 static int xscale_mmu(struct target *target, int *enabled)
3265 {
3266 struct xscale_common *xscale = target_to_xscale(target);
3267
3268 if (target->state != TARGET_HALTED)
3269 {
3270 LOG_ERROR("Target not halted");
3271 return ERROR_TARGET_INVALID;
3272 }
3273 *enabled = xscale->armv4_5_mmu.mmu_enabled;
3274 return ERROR_OK;
3275 }
3276
3277 COMMAND_HANDLER(xscale_handle_mmu_command)
3278 {
3279 struct target *target = get_current_target(CMD_CTX);
3280 struct xscale_common *xscale = target_to_xscale(target);
3281 int retval;
3282
3283 retval = xscale_verify_pointer(CMD_CTX, xscale);
3284 if (retval != ERROR_OK)
3285 return retval;
3286
3287 if (target->state != TARGET_HALTED)
3288 {
3289 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3290 return ERROR_OK;
3291 }
3292
3293 if (CMD_ARGC >= 1)
3294 {
3295 bool enable;
3296 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3297 if (enable)
3298 xscale_enable_mmu_caches(target, 1, 0, 0);
3299 else
3300 xscale_disable_mmu_caches(target, 1, 0, 0);
3301 xscale->armv4_5_mmu.mmu_enabled = enable;
3302 }
3303
3304 command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3305
3306 return ERROR_OK;
3307 }
3308
3309 COMMAND_HANDLER(xscale_handle_idcache_command)
3310 {
3311 struct target *target = get_current_target(CMD_CTX);
3312 struct xscale_common *xscale = target_to_xscale(target);
3313
3314 int retval = xscale_verify_pointer(CMD_CTX, xscale);
3315 if (retval != ERROR_OK)
3316 return retval;
3317
3318 if (target->state != TARGET_HALTED)
3319 {
3320 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3321 return ERROR_OK;
3322 }
3323
3324 bool icache = false;
3325 if (strcmp(CMD_NAME, "icache") == 0)
3326 icache = true;
3327 if (CMD_ARGC >= 1)
3328 {
3329 bool enable;
3330 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3331 if (icache) {
3332 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
3333 if (enable)
3334 xscale_enable_mmu_caches(target, 0, 0, 1);
3335 else
3336 xscale_disable_mmu_caches(target, 0, 0, 1);
3337 } else {
3338 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
3339 if (enable)
3340 xscale_enable_mmu_caches(target, 0, 1, 0);
3341 else
3342 xscale_disable_mmu_caches(target, 0, 1, 0);
3343 }
3344 }
3345
3346 bool enabled = icache ?
3347 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
3348 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
3349 const char *msg = enabled ? "enabled" : "disabled";
3350 command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
3351
3352 return ERROR_OK;
3353 }
3354
3355 COMMAND_HANDLER(xscale_handle_vector_catch_command)
3356 {
3357 struct target *target = get_current_target(CMD_CTX);
3358 struct xscale_common *xscale = target_to_xscale(target);
3359 int retval;
3360
3361 retval = xscale_verify_pointer(CMD_CTX, xscale);
3362 if (retval != ERROR_OK)
3363 return retval;
3364
3365 if (CMD_ARGC < 1)
3366 {
3367 command_print(CMD_CTX, "usage: xscale vector_catch [mask]");
3368 }
3369 else
3370 {
3371 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch);
3372 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3373 xscale_write_dcsr(target, -1, -1);
3374 }
3375
3376 command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3377
3378 return ERROR_OK;
3379 }
3380
3381
3382 COMMAND_HANDLER(xscale_handle_vector_table_command)
3383 {
3384 struct target *target = get_current_target(CMD_CTX);
3385 struct xscale_common *xscale = target_to_xscale(target);
3386 int err = 0;
3387 int retval;
3388
3389 retval = xscale_verify_pointer(CMD_CTX, xscale);
3390 if (retval != ERROR_OK)
3391 return retval;
3392
3393 if (CMD_ARGC == 0) /* print current settings */
3394 {
3395 int idx;
3396
3397 command_print(CMD_CTX, "active user-set static vectors:");
3398 for (idx = 1; idx < 8; idx++)
3399 if (xscale->static_low_vectors_set & (1 << idx))
3400 command_print(CMD_CTX, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
3401 for (idx = 1; idx < 8; idx++)
3402 if (xscale->static_high_vectors_set & (1 << idx))
3403 command_print(CMD_CTX, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
3404 return ERROR_OK;
3405 }
3406
3407 if (CMD_ARGC != 3)
3408 err = 1;
3409 else
3410 {
3411 int idx;
3412 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
3413 uint32_t vec;
3414 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
3415
3416 if (idx < 1 || idx >= 8)
3417 err = 1;
3418
3419 if (!err && strcmp(CMD_ARGV[0], "low") == 0)
3420 {
3421 xscale->static_low_vectors_set |= (1<<idx);
3422 xscale->static_low_vectors[idx] = vec;
3423 }
3424 else if (!err && (strcmp(CMD_ARGV[0], "high") == 0))
3425 {
3426 xscale->static_high_vectors_set |= (1<<idx);
3427 xscale->static_high_vectors[idx] = vec;
3428 }
3429 else
3430 err = 1;
3431 }
3432
3433 if (err)
3434 command_print(CMD_CTX, "usage: xscale vector_table <high|low> <index> <code>");
3435
3436 return ERROR_OK;
3437 }
3438
3439
3440 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
3441 {
3442 struct target *target = get_current_target(CMD_CTX);
3443 struct xscale_common *xscale = target_to_xscale(target);
3444 uint32_t dcsr_value;
3445 int retval;
3446
3447 retval = xscale_verify_pointer(CMD_CTX, xscale);
3448 if (retval != ERROR_OK)
3449 return retval;
3450
3451 if (target->state != TARGET_HALTED)
3452 {
3453 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3454 return ERROR_OK;
3455 }
3456
3457 if ((CMD_ARGC >= 1) && (strcmp("enable", CMD_ARGV[0]) == 0))
3458 {
3459 struct xscale_trace_data *td, *next_td;
3460 xscale->trace.buffer_enabled = 1;
3461
3462 /* free old trace data */
3463 td = xscale->trace.data;
3464 while (td)
3465 {
3466 next_td = td->next;
3467
3468 if (td->entries)
3469 free(td->entries);
3470 free(td);
3471 td = next_td;
3472 }
3473 xscale->trace.data = NULL;
3474 }
3475 else if ((CMD_ARGC >= 1) && (strcmp("disable", CMD_ARGV[0]) == 0))
3476 {
3477 xscale->trace.buffer_enabled = 0;
3478 }
3479
3480 if ((CMD_ARGC >= 2) && (strcmp("fill", CMD_ARGV[1]) == 0))
3481 {
3482 uint32_t fill = 1;
3483 if (CMD_ARGC >= 3)
3484 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], fill);
3485 xscale->trace.buffer_fill = fill;
3486 }
3487 else if ((CMD_ARGC >= 2) && (strcmp("wrap", CMD_ARGV[1]) == 0))
3488 {
3489 xscale->trace.buffer_fill = -1;
3490 }
3491
3492 command_print(CMD_CTX, "trace buffer %s (%s)",
3493 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3494 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3495
3496 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3497 if (xscale->trace.buffer_fill >= 0)
3498 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3499 else
3500 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3501
3502 return ERROR_OK;
3503 }
3504
3505 COMMAND_HANDLER(xscale_handle_trace_image_command)
3506 {
3507 struct target *target = get_current_target(CMD_CTX);
3508 struct xscale_common *xscale = target_to_xscale(target);
3509 int retval;
3510
3511 if (CMD_ARGC < 1)
3512 {
3513 command_print(CMD_CTX, "usage: xscale trace_image <file> [base address] [type]");
3514 return ERROR_OK;
3515 }
3516
3517 retval = xscale_verify_pointer(CMD_CTX, xscale);
3518 if (retval != ERROR_OK)
3519 return retval;
3520
3521 if (xscale->trace.image)
3522 {
3523 image_close(xscale->trace.image);
3524 free(xscale->trace.image);
3525 command_print(CMD_CTX, "previously loaded image found and closed");
3526 }
3527
3528 xscale->trace.image = malloc(sizeof(struct image));
3529 xscale->trace.image->base_address_set = 0;
3530 xscale->trace.image->start_address_set = 0;
3531
3532 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3533 if (CMD_ARGC >= 2)
3534 {
3535 xscale->trace.image->base_address_set = 1;
3536 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
3537 }
3538 else
3539 {
3540 xscale->trace.image->base_address_set = 0;
3541 }
3542
3543 if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
3544 {
3545 free(xscale->trace.image);
3546 xscale->trace.image = NULL;
3547 return ERROR_OK;
3548 }
3549
3550 return ERROR_OK;
3551 }
3552
3553 COMMAND_HANDLER(xscale_handle_dump_trace_command)
3554 {
3555 struct target *target = get_current_target(CMD_CTX);
3556 struct xscale_common *xscale = target_to_xscale(target);
3557 struct xscale_trace_data *trace_data;
3558 struct fileio file;
3559 int retval;
3560
3561 retval = xscale_verify_pointer(CMD_CTX, xscale);
3562 if (retval != ERROR_OK)
3563 return retval;
3564
3565 if (target->state != TARGET_HALTED)
3566 {
3567 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3568 return ERROR_OK;
3569 }
3570
3571 if (CMD_ARGC < 1)
3572 {
3573 command_print(CMD_CTX, "usage: xscale dump_trace <file>");
3574 return ERROR_OK;
3575 }
3576
3577 trace_data = xscale->trace.data;
3578
3579 if (!trace_data)
3580 {
3581 command_print(CMD_CTX, "no trace data collected");
3582 return ERROR_OK;
3583 }
3584
3585 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3586 {
3587 return ERROR_OK;
3588 }
3589
3590 while (trace_data)
3591 {
3592 int i;
3593
3594 fileio_write_u32(&file, trace_data->chkpt0);
3595 fileio_write_u32(&file, trace_data->chkpt1);
3596 fileio_write_u32(&file, trace_data->last_instruction);
3597 fileio_write_u32(&file, trace_data->depth);
3598
3599 for (i = 0; i < trace_data->depth; i++)
3600 fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3601
3602 trace_data = trace_data->next;
3603 }
3604
3605 fileio_close(&file);
3606
3607 return ERROR_OK;
3608 }
3609
3610 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
3611 {
3612 struct target *target = get_current_target(CMD_CTX);
3613 struct xscale_common *xscale = target_to_xscale(target);
3614 int retval;
3615
3616 retval = xscale_verify_pointer(CMD_CTX, xscale);
3617 if (retval != ERROR_OK)
3618 return retval;
3619
3620 xscale_analyze_trace(target, CMD_CTX);
3621
3622 return ERROR_OK;
3623 }
3624
3625 COMMAND_HANDLER(xscale_handle_cp15)
3626 {
3627 struct target *target = get_current_target(CMD_CTX);
3628 struct xscale_common *xscale = target_to_xscale(target);
3629 int retval;
3630
3631 retval = xscale_verify_pointer(CMD_CTX, xscale);
3632 if (retval != ERROR_OK)
3633 return retval;
3634
3635 if (target->state != TARGET_HALTED)
3636 {
3637 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3638 return ERROR_OK;
3639 }
3640 uint32_t reg_no = 0;
3641 struct reg *reg = NULL;
3642 if (CMD_ARGC > 0)
3643 {
3644 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
3645 /*translate from xscale cp15 register no to openocd register*/
3646 switch (reg_no)
3647 {
3648 case 0:
3649 reg_no = XSCALE_MAINID;
3650 break;
3651 case 1:
3652 reg_no = XSCALE_CTRL;
3653 break;
3654 case 2:
3655 reg_no = XSCALE_TTB;
3656 break;
3657 case 3:
3658 reg_no = XSCALE_DAC;
3659 break;
3660 case 5:
3661 reg_no = XSCALE_FSR;
3662 break;
3663 case 6:
3664 reg_no = XSCALE_FAR;
3665 break;
3666 case 13:
3667 reg_no = XSCALE_PID;
3668 break;
3669 case 15:
3670 reg_no = XSCALE_CPACCESS;
3671 break;
3672 default:
3673 command_print(CMD_CTX, "invalid register number");
3674 return ERROR_INVALID_ARGUMENTS;
3675 }
3676 reg = &xscale->reg_cache->reg_list[reg_no];
3677
3678 }
3679 if (CMD_ARGC == 1)
3680 {
3681 uint32_t value;
3682
3683 /* read cp15 control register */
3684 xscale_get_reg(reg);
3685 value = buf_get_u32(reg->value, 0, 32);
3686 command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
3687 }
3688 else if (CMD_ARGC == 2)
3689 {
3690 uint32_t value;
3691 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
3692
3693 /* send CP write request (command 0x41) */
3694 xscale_send_u32(target, 0x41);
3695
3696 /* send CP register number */
3697 xscale_send_u32(target, reg_no);
3698
3699 /* send CP register value */
3700 xscale_send_u32(target, value);
3701
3702 /* execute cpwait to ensure outstanding operations complete */
3703 xscale_send_u32(target, 0x53);
3704 }
3705 else
3706 {
3707 command_print(CMD_CTX, "usage: cp15 [register]<, [value]>");
3708 }
3709
3710 return ERROR_OK;
3711 }
3712
3713 static const struct command_registration xscale_exec_command_handlers[] = {
3714 {
3715 .name = "cache_info",
3716 .handler = xscale_handle_cache_info_command,
3717 .mode = COMMAND_EXEC,
3718 .help = "display information about CPU caches",
3719 },
3720 {
3721 .name = "mmu",
3722 .handler = xscale_handle_mmu_command,
3723 .mode = COMMAND_EXEC,
3724 .help = "enable or disable the MMU",
3725 .usage = "['enable'|'disable']",
3726 },
3727 {
3728 .name = "icache",
3729 .handler = xscale_handle_idcache_command,
3730 .mode = COMMAND_EXEC,
3731 .help = "display ICache state, optionally enabling or "
3732 "disabling it",
3733 .usage = "['enable'|'disable']",
3734 },
3735 {
3736 .name = "dcache",
3737 .handler = xscale_handle_idcache_command,
3738 .mode = COMMAND_EXEC,
3739 .help = "display DCache state, optionally enabling or "
3740 "disabling it",
3741 .usage = "['enable'|'disable']",
3742 },
3743 {
3744 .name = "vector_catch",
3745 .handler = xscale_handle_vector_catch_command,
3746 .mode = COMMAND_EXEC,
3747 .help = "set or display 8-bit mask of vectors "
3748 "that should trigger debug entry",
3749 .usage = "[mask]",
3750 },
3751 {
3752 .name = "vector_table",
3753 .handler = xscale_handle_vector_table_command,
3754 .mode = COMMAND_EXEC,
3755 .help = "set vector table entry in mini-ICache, "
3756 "or display current tables",
3757 .usage = "[('high'|'low') index code]",
3758 },
3759 {
3760 .name = "trace_buffer",
3761 .handler = xscale_handle_trace_buffer_command,
3762 .mode = COMMAND_EXEC,
3763 .help = "display trace buffer status, enable or disable "
3764 "tracing, and optionally reconfigure trace mode",
3765 .usage = "['enable'|'disable' ['fill' number|'wrap']]",
3766 },
3767 {
3768 .name = "dump_trace",
3769 .handler = xscale_handle_dump_trace_command,
3770 .mode = COMMAND_EXEC,
3771 .help = "dump content of trace buffer to file",
3772 .usage = "filename",
3773 },
3774 {
3775 .name = "analyze_trace",
3776 .handler = xscale_handle_analyze_trace_buffer_command,
3777 .mode = COMMAND_EXEC,
3778 .help = "analyze content of trace buffer",
3779 .usage = "",
3780 },
3781 {
3782 .name = "trace_image",
3783 .handler = xscale_handle_trace_image_command,
3784 .mode = COMMAND_EXEC,
3785 .help = "load image from file to address (default 0)",
3786 .usage = "filename [offset [filetype]]",
3787 },
3788 {
3789 .name = "cp15",
3790 .handler = xscale_handle_cp15,
3791 .mode = COMMAND_EXEC,
3792 .help = "Read or write coprocessor 15 register.",
3793 .usage = "register [value]",
3794 },
3795 COMMAND_REGISTRATION_DONE
3796 };
3797 static const struct command_registration xscale_any_command_handlers[] = {
3798 {
3799 .name = "debug_handler",
3800 .handler = xscale_handle_debug_handler_command,
3801 .mode = COMMAND_ANY,
3802 .help = "Change address used for debug handler.",
3803 .usage = "target address",
3804 },
3805 {
3806 .name = "cache_clean_address",
3807 .handler = xscale_handle_cache_clean_address_command,
3808 .mode = COMMAND_ANY,
3809 .help = "Change address used for cleaning data cache.",
3810 .usage = "address",
3811 },
3812 {
3813 .chain = xscale_exec_command_handlers,
3814 },
3815 COMMAND_REGISTRATION_DONE
3816 };
3817 static const struct command_registration xscale_command_handlers[] = {
3818 {
3819 .chain = arm_command_handlers,
3820 },
3821 {
3822 .name = "xscale",
3823 .mode = COMMAND_ANY,
3824 .help = "xscale command group",
3825 .chain = xscale_any_command_handlers,
3826 },
3827 COMMAND_REGISTRATION_DONE
3828 };
3829
3830 struct target_type xscale_target =
3831 {
3832 .name = "xscale",
3833
3834 .poll = xscale_poll,
3835 .arch_state = xscale_arch_state,
3836
3837 .target_request_data = NULL,
3838
3839 .halt = xscale_halt,
3840 .resume = xscale_resume,
3841 .step = xscale_step,
3842
3843 .assert_reset = xscale_assert_reset,
3844 .deassert_reset = xscale_deassert_reset,
3845 .soft_reset_halt = NULL,
3846
3847 /* REVISIT on some cores, allow exporting iwmmxt registers ... */
3848 .get_gdb_reg_list = arm_get_gdb_reg_list,
3849
3850 .read_memory = xscale_read_memory,
3851 .read_phys_memory = xscale_read_phys_memory,
3852 .write_memory = xscale_write_memory,
3853 .write_phys_memory = xscale_write_phys_memory,
3854 .bulk_write_memory = xscale_bulk_write_memory,
3855
3856 .checksum_memory = arm_checksum_memory,
3857 .blank_check_memory = arm_blank_check_memory,
3858
3859 .run_algorithm = armv4_5_run_algorithm,
3860
3861 .add_breakpoint = xscale_add_breakpoint,
3862 .remove_breakpoint = xscale_remove_breakpoint,
3863 .add_watchpoint = xscale_add_watchpoint,
3864 .remove_watchpoint = xscale_remove_watchpoint,
3865
3866 .commands = xscale_command_handlers,
3867 .target_create = xscale_target_create,
3868 .init_target = xscale_init_target,
3869
3870 .virt2phys = xscale_virt2phys,
3871 .mmu = xscale_mmu
3872 };
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