1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "breakpoints.h"
32 #include "target_type.h"
34 #include "arm_simulator.h"
35 #include "arm_disassembler.h"
36 #include "time_support.h"
42 * Important XScale documents available as of October 2009 include:
44 * Intel XScale® Core Developer’s Manual, January 2004
45 * Order Number: 273473-002
46 * This has a chapter detailing debug facilities, and punts some
47 * details to chip-specific microarchitecture documents.
49 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
50 * Document Number: 273539-005
51 * Less detailed than the developer's manual, but summarizes those
52 * missing details (for most XScales) and gives LOTS of notes about
53 * debugger/handler interaction issues. Presents a simpler reset
54 * and load-handler sequence than the arch doc. (Note, OpenOCD
55 * doesn't currently support "Hot-Debug" as defined there.)
57 * Chip-specific microarchitecture documents may also be useful.
61 /* forward declarations */
62 static int xscale_resume(struct target
*, int current
,
63 uint32_t address
, int handle_breakpoints
, int debug_execution
);
64 static int xscale_debug_entry(struct target
*);
65 static int xscale_restore_context(struct target
*);
66 static int xscale_get_reg(struct reg
*reg
);
67 static int xscale_set_reg(struct reg
*reg
, uint8_t *buf
);
68 static int xscale_set_breakpoint(struct target
*, struct breakpoint
*);
69 static int xscale_set_watchpoint(struct target
*, struct watchpoint
*);
70 static int xscale_unset_breakpoint(struct target
*, struct breakpoint
*);
71 static int xscale_read_trace(struct target
*);
74 /* This XScale "debug handler" is loaded into the processor's
75 * mini-ICache, which is 2K of code writable only via JTAG.
77 * FIXME the OpenOCD "bin2char" utility currently doesn't handle
78 * binary files cleanly. It's string oriented, and terminates them
79 * with a NUL character. Better would be to generate the constants
80 * and let other code decide names, scoping, and other housekeeping.
82 static /* unsigned const char xscale_debug_handler[] = ... */
83 #include "xscale_debug.h"
85 static char *const xscale_reg_list
[] =
87 "XSCALE_MAINID", /* 0 */
97 "XSCALE_IBCR0", /* 10 */
107 "XSCALE_RX", /* 20 */
111 static const struct xscale_reg xscale_reg_arch_info
[] =
113 {XSCALE_MAINID
, NULL
},
114 {XSCALE_CACHETYPE
, NULL
},
116 {XSCALE_AUXCTRL
, NULL
},
122 {XSCALE_CPACCESS
, NULL
},
123 {XSCALE_IBCR0
, NULL
},
124 {XSCALE_IBCR1
, NULL
},
127 {XSCALE_DBCON
, NULL
},
128 {XSCALE_TBREG
, NULL
},
129 {XSCALE_CHKPT0
, NULL
},
130 {XSCALE_CHKPT1
, NULL
},
131 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
132 {-1, NULL
}, /* TX accessed via JTAG */
133 {-1, NULL
}, /* RX accessed via JTAG */
134 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
137 /* convenience wrapper to access XScale specific registers */
138 static int xscale_set_reg_u32(struct reg
*reg
, uint32_t value
)
142 buf_set_u32(buf
, 0, 32, value
);
144 return xscale_set_reg(reg
, buf
);
147 static const char xscale_not
[] = "target is not an XScale";
149 static int xscale_verify_pointer(struct command_context
*cmd_ctx
,
150 struct xscale_common
*xscale
)
152 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
153 command_print(cmd_ctx
, xscale_not
);
154 return ERROR_TARGET_INVALID
;
159 static int xscale_jtag_set_instr(struct jtag_tap
*tap
, uint32_t new_instr
)
164 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
166 struct scan_field field
;
169 memset(&field
, 0, sizeof field
);
171 field
.num_bits
= tap
->ir_length
;
172 field
.out_value
= scratch
;
173 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
175 jtag_add_ir_scan(1, &field
, jtag_get_end_state());
181 static int xscale_read_dcsr(struct target
*target
)
183 struct xscale_common
*xscale
= target_to_xscale(target
);
185 struct scan_field fields
[3];
186 uint8_t field0
= 0x0;
187 uint8_t field0_check_value
= 0x2;
188 uint8_t field0_check_mask
= 0x7;
189 uint8_t field2
= 0x0;
190 uint8_t field2_check_value
= 0x0;
191 uint8_t field2_check_mask
= 0x1;
193 jtag_set_end_state(TAP_DRPAUSE
);
194 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
196 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
197 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
199 memset(&fields
, 0, sizeof fields
);
201 fields
[0].tap
= target
->tap
;
202 fields
[0].num_bits
= 3;
203 fields
[0].out_value
= &field0
;
205 fields
[0].in_value
= &tmp
;
207 fields
[1].tap
= target
->tap
;
208 fields
[1].num_bits
= 32;
209 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
211 fields
[2].tap
= target
->tap
;
212 fields
[2].num_bits
= 1;
213 fields
[2].out_value
= &field2
;
215 fields
[2].in_value
= &tmp2
;
217 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
219 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
220 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
222 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
224 LOG_ERROR("JTAG error while reading DCSR");
228 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
229 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
231 /* write the register with the value we just read
232 * on this second pass, only the first bit of field0 is guaranteed to be 0)
234 field0_check_mask
= 0x1;
235 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
236 fields
[1].in_value
= NULL
;
238 jtag_set_end_state(TAP_IDLE
);
240 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
242 /* DANGER!!! this must be here. It will make sure that the arguments
243 * to jtag_set_check_value() does not go out of scope! */
244 return jtag_execute_queue();
248 static void xscale_getbuf(jtag_callback_data_t arg
)
250 uint8_t *in
= (uint8_t *)arg
;
251 *((uint32_t *)in
) = buf_get_u32(in
, 0, 32);
254 static int xscale_receive(struct target
*target
, uint32_t *buffer
, int num_words
)
257 return ERROR_INVALID_ARGUMENTS
;
259 int retval
= ERROR_OK
;
261 struct scan_field fields
[3];
262 uint8_t *field0
= malloc(num_words
* 1);
263 uint8_t field0_check_value
= 0x2;
264 uint8_t field0_check_mask
= 0x6;
265 uint32_t *field1
= malloc(num_words
* 4);
266 uint8_t field2_check_value
= 0x0;
267 uint8_t field2_check_mask
= 0x1;
269 int words_scheduled
= 0;
272 path
[0] = TAP_DRSELECT
;
273 path
[1] = TAP_DRCAPTURE
;
274 path
[2] = TAP_DRSHIFT
;
276 memset(&fields
, 0, sizeof fields
);
278 fields
[0].tap
= target
->tap
;
279 fields
[0].num_bits
= 3;
280 fields
[0].check_value
= &field0_check_value
;
281 fields
[0].check_mask
= &field0_check_mask
;
283 fields
[1].tap
= target
->tap
;
284 fields
[1].num_bits
= 32;
286 fields
[2].tap
= target
->tap
;
287 fields
[2].num_bits
= 1;
288 fields
[2].check_value
= &field2_check_value
;
289 fields
[2].check_mask
= &field2_check_mask
;
291 jtag_set_end_state(TAP_IDLE
);
292 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGTX
);
293 jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
295 /* repeat until all words have been collected */
297 while (words_done
< num_words
)
301 for (i
= words_done
; i
< num_words
; i
++)
303 fields
[0].in_value
= &field0
[i
];
305 jtag_add_pathmove(3, path
);
307 fields
[1].in_value
= (uint8_t *)(field1
+ i
);
309 jtag_add_dr_scan_check(3, fields
, jtag_set_end_state(TAP_IDLE
));
311 jtag_add_callback(xscale_getbuf
, (jtag_callback_data_t
)(field1
+ i
));
316 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
318 LOG_ERROR("JTAG error while receiving data from debug handler");
322 /* examine results */
323 for (i
= words_done
; i
< num_words
; i
++)
325 if (!(field0
[0] & 1))
327 /* move backwards if necessary */
329 for (j
= i
; j
< num_words
- 1; j
++)
331 field0
[j
] = field0
[j
+ 1];
332 field1
[j
] = field1
[j
+ 1];
337 if (words_scheduled
== 0)
339 if (attempts
++==1000)
341 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
342 retval
= ERROR_TARGET_TIMEOUT
;
347 words_done
+= words_scheduled
;
350 for (i
= 0; i
< num_words
; i
++)
351 *(buffer
++) = buf_get_u32((uint8_t*)&field1
[i
], 0, 32);
358 static int xscale_read_tx(struct target
*target
, int consume
)
360 struct xscale_common
*xscale
= target_to_xscale(target
);
362 tap_state_t noconsume_path
[6];
364 struct timeval timeout
, now
;
365 struct scan_field fields
[3];
366 uint8_t field0_in
= 0x0;
367 uint8_t field0_check_value
= 0x2;
368 uint8_t field0_check_mask
= 0x6;
369 uint8_t field2_check_value
= 0x0;
370 uint8_t field2_check_mask
= 0x1;
372 jtag_set_end_state(TAP_IDLE
);
374 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGTX
);
376 path
[0] = TAP_DRSELECT
;
377 path
[1] = TAP_DRCAPTURE
;
378 path
[2] = TAP_DRSHIFT
;
380 noconsume_path
[0] = TAP_DRSELECT
;
381 noconsume_path
[1] = TAP_DRCAPTURE
;
382 noconsume_path
[2] = TAP_DREXIT1
;
383 noconsume_path
[3] = TAP_DRPAUSE
;
384 noconsume_path
[4] = TAP_DREXIT2
;
385 noconsume_path
[5] = TAP_DRSHIFT
;
387 memset(&fields
, 0, sizeof fields
);
389 fields
[0].tap
= target
->tap
;
390 fields
[0].num_bits
= 3;
391 fields
[0].in_value
= &field0_in
;
393 fields
[1].tap
= target
->tap
;
394 fields
[1].num_bits
= 32;
395 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
397 fields
[2].tap
= target
->tap
;
398 fields
[2].num_bits
= 1;
400 fields
[2].in_value
= &tmp
;
402 gettimeofday(&timeout
, NULL
);
403 timeval_add_time(&timeout
, 1, 0);
407 /* if we want to consume the register content (i.e. clear TX_READY),
408 * we have to go straight from Capture-DR to Shift-DR
409 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
412 jtag_add_pathmove(3, path
);
415 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
418 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
420 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
421 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
423 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
425 LOG_ERROR("JTAG error while reading TX");
426 return ERROR_TARGET_TIMEOUT
;
429 gettimeofday(&now
, NULL
);
430 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
432 LOG_ERROR("time out reading TX register");
433 return ERROR_TARGET_TIMEOUT
;
435 if (!((!(field0_in
& 1)) && consume
))
439 if (debug_level
>= 3)
441 LOG_DEBUG("waiting 100ms");
442 alive_sleep(100); /* avoid flooding the logs */
450 if (!(field0_in
& 1))
451 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
456 static int xscale_write_rx(struct target
*target
)
458 struct xscale_common
*xscale
= target_to_xscale(target
);
460 struct timeval timeout
, now
;
461 struct scan_field fields
[3];
462 uint8_t field0_out
= 0x0;
463 uint8_t field0_in
= 0x0;
464 uint8_t field0_check_value
= 0x2;
465 uint8_t field0_check_mask
= 0x6;
466 uint8_t field2
= 0x0;
467 uint8_t field2_check_value
= 0x0;
468 uint8_t field2_check_mask
= 0x1;
470 jtag_set_end_state(TAP_IDLE
);
472 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGRX
);
474 memset(&fields
, 0, sizeof fields
);
476 fields
[0].tap
= target
->tap
;
477 fields
[0].num_bits
= 3;
478 fields
[0].out_value
= &field0_out
;
479 fields
[0].in_value
= &field0_in
;
481 fields
[1].tap
= target
->tap
;
482 fields
[1].num_bits
= 32;
483 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
485 fields
[2].tap
= target
->tap
;
486 fields
[2].num_bits
= 1;
487 fields
[2].out_value
= &field2
;
489 fields
[2].in_value
= &tmp
;
491 gettimeofday(&timeout
, NULL
);
492 timeval_add_time(&timeout
, 1, 0);
494 /* poll until rx_read is low */
495 LOG_DEBUG("polling RX");
498 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
500 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
501 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
503 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
505 LOG_ERROR("JTAG error while writing RX");
509 gettimeofday(&now
, NULL
);
510 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
512 LOG_ERROR("time out writing RX register");
513 return ERROR_TARGET_TIMEOUT
;
515 if (!(field0_in
& 1))
517 if (debug_level
>= 3)
519 LOG_DEBUG("waiting 100ms");
520 alive_sleep(100); /* avoid flooding the logs */
530 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
532 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
534 LOG_ERROR("JTAG error while writing RX");
541 /* send count elements of size byte to the debug handler */
542 static int xscale_send(struct target
*target
, uint8_t *buffer
, int count
, int size
)
549 jtag_set_end_state(TAP_IDLE
);
551 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGRX
);
558 int endianness
= target
->endianness
;
559 while (done_count
++ < count
)
564 if (endianness
== TARGET_LITTLE_ENDIAN
)
566 t
[1]=le_to_h_u32(buffer
);
569 t
[1]=be_to_h_u32(buffer
);
573 if (endianness
== TARGET_LITTLE_ENDIAN
)
575 t
[1]=le_to_h_u16(buffer
);
578 t
[1]=be_to_h_u16(buffer
);
585 LOG_ERROR("BUG: size neither 4, 2 nor 1");
586 return ERROR_INVALID_ARGUMENTS
;
588 jtag_add_dr_out(target
->tap
,
592 jtag_set_end_state(TAP_IDLE
));
596 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
598 LOG_ERROR("JTAG error while sending data to debug handler");
605 static int xscale_send_u32(struct target
*target
, uint32_t value
)
607 struct xscale_common
*xscale
= target_to_xscale(target
);
609 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
610 return xscale_write_rx(target
);
613 static int xscale_write_dcsr(struct target
*target
, int hold_rst
, int ext_dbg_brk
)
615 struct xscale_common
*xscale
= target_to_xscale(target
);
617 struct scan_field fields
[3];
618 uint8_t field0
= 0x0;
619 uint8_t field0_check_value
= 0x2;
620 uint8_t field0_check_mask
= 0x7;
621 uint8_t field2
= 0x0;
622 uint8_t field2_check_value
= 0x0;
623 uint8_t field2_check_mask
= 0x1;
626 xscale
->hold_rst
= hold_rst
;
628 if (ext_dbg_brk
!= -1)
629 xscale
->external_debug_break
= ext_dbg_brk
;
631 jtag_set_end_state(TAP_IDLE
);
632 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
634 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
635 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
637 memset(&fields
, 0, sizeof fields
);
639 fields
[0].tap
= target
->tap
;
640 fields
[0].num_bits
= 3;
641 fields
[0].out_value
= &field0
;
643 fields
[0].in_value
= &tmp
;
645 fields
[1].tap
= target
->tap
;
646 fields
[1].num_bits
= 32;
647 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
649 fields
[2].tap
= target
->tap
;
650 fields
[2].num_bits
= 1;
651 fields
[2].out_value
= &field2
;
653 fields
[2].in_value
= &tmp2
;
655 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
657 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
658 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
660 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
662 LOG_ERROR("JTAG error while writing DCSR");
666 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
667 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
672 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
673 static unsigned int parity (unsigned int v
)
675 // unsigned int ov = v;
680 // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
681 return (0x6996 >> v
) & 1;
684 static int xscale_load_ic(struct target
*target
, uint32_t va
, uint32_t buffer
[8])
689 struct scan_field fields
[2];
691 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32
"", va
);
694 jtag_set_end_state(TAP_IDLE
);
695 xscale_jtag_set_instr(target
->tap
, XSCALE_LDIC
);
697 /* CMD is b011 to load a cacheline into the Mini ICache.
698 * Loading into the main ICache is deprecated, and unused.
699 * It's followed by three zero bits, and 27 address bits.
701 buf_set_u32(&cmd
, 0, 6, 0x3);
703 /* virtual address of desired cache line */
704 buf_set_u32(packet
, 0, 27, va
>> 5);
706 memset(&fields
, 0, sizeof fields
);
708 fields
[0].tap
= target
->tap
;
709 fields
[0].num_bits
= 6;
710 fields
[0].out_value
= &cmd
;
712 fields
[1].tap
= target
->tap
;
713 fields
[1].num_bits
= 27;
714 fields
[1].out_value
= packet
;
716 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
718 /* rest of packet is a cacheline: 8 instructions, with parity */
719 fields
[0].num_bits
= 32;
720 fields
[0].out_value
= packet
;
722 fields
[1].num_bits
= 1;
723 fields
[1].out_value
= &cmd
;
725 for (word
= 0; word
< 8; word
++)
727 buf_set_u32(packet
, 0, 32, buffer
[word
]);
730 memcpy(&value
, packet
, sizeof(uint32_t));
733 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
736 return jtag_execute_queue();
739 static int xscale_invalidate_ic_line(struct target
*target
, uint32_t va
)
743 struct scan_field fields
[2];
745 jtag_set_end_state(TAP_IDLE
);
746 xscale_jtag_set_instr(target
->tap
, XSCALE_LDIC
);
748 /* CMD for invalidate IC line b000, bits [6:4] b000 */
749 buf_set_u32(&cmd
, 0, 6, 0x0);
751 /* virtual address of desired cache line */
752 buf_set_u32(packet
, 0, 27, va
>> 5);
754 memset(&fields
, 0, sizeof fields
);
756 fields
[0].tap
= target
->tap
;
757 fields
[0].num_bits
= 6;
758 fields
[0].out_value
= &cmd
;
760 fields
[1].tap
= target
->tap
;
761 fields
[1].num_bits
= 27;
762 fields
[1].out_value
= packet
;
764 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
769 static int xscale_update_vectors(struct target
*target
)
771 struct xscale_common
*xscale
= target_to_xscale(target
);
775 uint32_t low_reset_branch
, high_reset_branch
;
777 for (i
= 1; i
< 8; i
++)
779 /* if there's a static vector specified for this exception, override */
780 if (xscale
->static_high_vectors_set
& (1 << i
))
782 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
786 retval
= target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
787 if (retval
== ERROR_TARGET_TIMEOUT
)
789 if (retval
!= ERROR_OK
)
791 /* Some of these reads will fail as part of normal execution */
792 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
797 for (i
= 1; i
< 8; i
++)
799 if (xscale
->static_low_vectors_set
& (1 << i
))
801 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
805 retval
= target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
806 if (retval
== ERROR_TARGET_TIMEOUT
)
808 if (retval
!= ERROR_OK
)
810 /* Some of these reads will fail as part of normal execution */
811 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
816 /* calculate branches to debug handler */
817 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
818 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
820 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
821 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
823 /* invalidate and load exception vectors in mini i-cache */
824 xscale_invalidate_ic_line(target
, 0x0);
825 xscale_invalidate_ic_line(target
, 0xffff0000);
827 xscale_load_ic(target
, 0x0, xscale
->low_vectors
);
828 xscale_load_ic(target
, 0xffff0000, xscale
->high_vectors
);
833 static int xscale_arch_state(struct target
*target
)
835 struct xscale_common
*xscale
= target_to_xscale(target
);
836 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
838 static const char *state
[] =
840 "disabled", "enabled"
843 static const char *arch_dbg_reason
[] =
845 "", "\n(processor reset)", "\n(trace buffer full)"
848 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
850 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
851 return ERROR_INVALID_ARGUMENTS
;
854 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
855 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
856 "MMU: %s, D-Cache: %s, I-Cache: %s"
858 armv4_5_state_strings
[armv4_5
->core_state
],
859 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
860 arm_mode_name(armv4_5
->core_mode
),
861 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
862 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
863 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
864 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
865 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
866 arch_dbg_reason
[xscale
->arch_debug_reason
]);
871 static int xscale_poll(struct target
*target
)
873 int retval
= ERROR_OK
;
875 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
877 enum target_state previous_state
= target
->state
;
878 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
881 /* there's data to read from the tx register, we entered debug state */
882 target
->state
= TARGET_HALTED
;
884 /* process debug entry, fetching current mode regs */
885 retval
= xscale_debug_entry(target
);
887 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
889 LOG_USER("error while polling TX register, reset CPU");
890 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
891 target
->state
= TARGET_HALTED
;
894 /* debug_entry could have overwritten target state (i.e. immediate resume)
895 * don't signal event handlers in that case
897 if (target
->state
!= TARGET_HALTED
)
900 /* if target was running, signal that we halted
901 * otherwise we reentered from debug execution */
902 if (previous_state
== TARGET_RUNNING
)
903 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
905 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
911 static int xscale_debug_entry(struct target
*target
)
913 struct xscale_common
*xscale
= target_to_xscale(target
);
914 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
921 /* clear external dbg break (will be written on next DCSR read) */
922 xscale
->external_debug_break
= 0;
923 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
926 /* get r0, pc, r1 to r7 and cpsr */
927 if ((retval
= xscale_receive(target
, buffer
, 10)) != ERROR_OK
)
930 /* move r0 from buffer to register cache */
931 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
932 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
933 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
934 LOG_DEBUG("r0: 0x%8.8" PRIx32
"", buffer
[0]);
936 /* move pc from buffer to register cache */
937 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
938 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
939 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
940 LOG_DEBUG("pc: 0x%8.8" PRIx32
"", buffer
[1]);
942 /* move data from buffer to register cache */
943 for (i
= 1; i
<= 7; i
++)
945 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
946 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
947 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
948 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, buffer
[i
+ 1]);
951 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
952 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
953 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
954 LOG_DEBUG("cpsr: 0x%8.8" PRIx32
"", buffer
[9]);
956 armv4_5
->core_mode
= buffer
[9] & 0x1f;
957 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
959 target
->state
= TARGET_UNKNOWN
;
960 LOG_ERROR("cpsr contains invalid mode value - communication failure");
961 return ERROR_TARGET_FAILURE
;
963 LOG_DEBUG("target entered debug state in %s mode",
964 arm_mode_name(armv4_5
->core_mode
));
966 if (buffer
[9] & 0x20)
967 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
969 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
972 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
975 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
976 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
978 xscale_receive(target
, buffer
, 8);
979 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
980 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
981 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
985 /* r8 to r14, but no spsr */
986 xscale_receive(target
, buffer
, 7);
989 /* move data from buffer to register cache */
990 for (i
= 8; i
<= 14; i
++)
992 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
993 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
994 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
997 /* examine debug reason */
998 xscale_read_dcsr(target
);
999 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1001 /* stored PC (for calculating fixup) */
1002 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1006 case 0x0: /* Processor reset */
1007 target
->debug_reason
= DBG_REASON_DBGRQ
;
1008 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1011 case 0x1: /* Instruction breakpoint hit */
1012 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1013 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1016 case 0x2: /* Data breakpoint hit */
1017 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1018 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1021 case 0x3: /* BKPT instruction executed */
1022 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1023 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1026 case 0x4: /* Ext. debug event */
1027 target
->debug_reason
= DBG_REASON_DBGRQ
;
1028 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1031 case 0x5: /* Vector trap occured */
1032 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1033 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1036 case 0x6: /* Trace buffer full break */
1037 target
->debug_reason
= DBG_REASON_DBGRQ
;
1038 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1041 case 0x7: /* Reserved (may flag Hot-Debug support) */
1043 LOG_ERROR("Method of Entry is 'Reserved'");
1048 /* apply PC fixup */
1049 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1051 /* on the first debug entry, identify cache type */
1052 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1054 uint32_t cache_type_reg
;
1056 /* read cp15 cache type register */
1057 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1058 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1060 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1063 /* examine MMU and Cache settings */
1064 /* read cp15 control register */
1065 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1066 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1067 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1068 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1069 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1071 /* tracing enabled, read collected trace data */
1072 if (xscale
->trace
.buffer_enabled
)
1074 xscale_read_trace(target
);
1075 xscale
->trace
.buffer_fill
--;
1077 /* resume if we're still collecting trace data */
1078 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1079 && (xscale
->trace
.buffer_fill
> 0))
1081 xscale_resume(target
, 1, 0x0, 1, 0);
1085 xscale
->trace
.buffer_enabled
= 0;
1092 static int xscale_halt(struct target
*target
)
1094 struct xscale_common
*xscale
= target_to_xscale(target
);
1096 LOG_DEBUG("target->state: %s",
1097 target_state_name(target
));
1099 if (target
->state
== TARGET_HALTED
)
1101 LOG_DEBUG("target was already halted");
1104 else if (target
->state
== TARGET_UNKNOWN
)
1106 /* this must not happen for a xscale target */
1107 LOG_ERROR("target was in unknown state when halt was requested");
1108 return ERROR_TARGET_INVALID
;
1110 else if (target
->state
== TARGET_RESET
)
1112 LOG_DEBUG("target->state == TARGET_RESET");
1116 /* assert external dbg break */
1117 xscale
->external_debug_break
= 1;
1118 xscale_read_dcsr(target
);
1120 target
->debug_reason
= DBG_REASON_DBGRQ
;
1126 static int xscale_enable_single_step(struct target
*target
, uint32_t next_pc
)
1128 struct xscale_common
*xscale
= target_to_xscale(target
);
1129 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1132 if (xscale
->ibcr0_used
)
1134 struct breakpoint
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1138 xscale_unset_breakpoint(target
, ibcr0_bp
);
1142 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1147 if ((retval
= xscale_set_reg_u32(ibcr0
, next_pc
| 0x1)) != ERROR_OK
)
1153 static int xscale_disable_single_step(struct target
*target
)
1155 struct xscale_common
*xscale
= target_to_xscale(target
);
1156 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1159 if ((retval
= xscale_set_reg_u32(ibcr0
, 0x0)) != ERROR_OK
)
1165 static void xscale_enable_watchpoints(struct target
*target
)
1167 struct watchpoint
*watchpoint
= target
->watchpoints
;
1171 if (watchpoint
->set
== 0)
1172 xscale_set_watchpoint(target
, watchpoint
);
1173 watchpoint
= watchpoint
->next
;
1177 static void xscale_enable_breakpoints(struct target
*target
)
1179 struct breakpoint
*breakpoint
= target
->breakpoints
;
1181 /* set any pending breakpoints */
1184 if (breakpoint
->set
== 0)
1185 xscale_set_breakpoint(target
, breakpoint
);
1186 breakpoint
= breakpoint
->next
;
1190 static int xscale_resume(struct target
*target
, int current
,
1191 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1193 struct xscale_common
*xscale
= target_to_xscale(target
);
1194 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
1195 struct breakpoint
*breakpoint
= target
->breakpoints
;
1196 uint32_t current_pc
;
1202 if (target
->state
!= TARGET_HALTED
)
1204 LOG_WARNING("target not halted");
1205 return ERROR_TARGET_NOT_HALTED
;
1208 if (!debug_execution
)
1210 target_free_all_working_areas(target
);
1213 /* update vector tables */
1214 if ((retval
= xscale_update_vectors(target
)) != ERROR_OK
)
1217 /* current = 1: continue on current pc, otherwise continue at <address> */
1219 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1221 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1223 /* if we're at the reset vector, we have to simulate the branch */
1224 if (current_pc
== 0x0)
1226 arm_simulate_step(target
, NULL
);
1227 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1230 /* the front-end may request us not to handle breakpoints */
1231 if (handle_breakpoints
)
1233 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1237 /* there's a breakpoint at the current PC, we have to step over it */
1238 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1239 xscale_unset_breakpoint(target
, breakpoint
);
1241 /* calculate PC of next instruction */
1242 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1244 uint32_t current_opcode
;
1245 target_read_u32(target
, current_pc
, ¤t_opcode
);
1246 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1249 LOG_DEBUG("enable single-step");
1250 xscale_enable_single_step(target
, next_pc
);
1252 /* restore banked registers */
1253 xscale_restore_context(target
);
1255 /* send resume request (command 0x30 or 0x31)
1256 * clean the trace buffer if it is to be enabled (0x62) */
1257 if (xscale
->trace
.buffer_enabled
)
1259 xscale_send_u32(target
, 0x62);
1260 xscale_send_u32(target
, 0x31);
1263 xscale_send_u32(target
, 0x30);
1266 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1267 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1269 for (i
= 7; i
>= 0; i
--)
1272 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1273 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1277 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1278 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1280 /* wait for and process debug entry */
1281 xscale_debug_entry(target
);
1283 LOG_DEBUG("disable single-step");
1284 xscale_disable_single_step(target
);
1286 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1287 xscale_set_breakpoint(target
, breakpoint
);
1291 /* enable any pending breakpoints and watchpoints */
1292 xscale_enable_breakpoints(target
);
1293 xscale_enable_watchpoints(target
);
1295 /* restore banked registers */
1296 xscale_restore_context(target
);
1298 /* send resume request (command 0x30 or 0x31)
1299 * clean the trace buffer if it is to be enabled (0x62) */
1300 if (xscale
->trace
.buffer_enabled
)
1302 xscale_send_u32(target
, 0x62);
1303 xscale_send_u32(target
, 0x31);
1306 xscale_send_u32(target
, 0x30);
1309 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1310 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1312 for (i
= 7; i
>= 0; i
--)
1315 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1316 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1320 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1321 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1323 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1325 if (!debug_execution
)
1327 /* registers are now invalid */
1328 armv4_5_invalidate_core_regs(target
);
1329 target
->state
= TARGET_RUNNING
;
1330 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1334 target
->state
= TARGET_DEBUG_RUNNING
;
1335 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1338 LOG_DEBUG("target resumed");
1343 static int xscale_step_inner(struct target
*target
, int current
,
1344 uint32_t address
, int handle_breakpoints
)
1346 struct xscale_common
*xscale
= target_to_xscale(target
);
1347 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
1352 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1354 /* calculate PC of next instruction */
1355 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1357 uint32_t current_opcode
, current_pc
;
1358 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1360 target_read_u32(target
, current_pc
, ¤t_opcode
);
1361 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1365 LOG_DEBUG("enable single-step");
1366 if ((retval
= xscale_enable_single_step(target
, next_pc
)) != ERROR_OK
)
1369 /* restore banked registers */
1370 if ((retval
= xscale_restore_context(target
)) != ERROR_OK
)
1373 /* send resume request (command 0x30 or 0x31)
1374 * clean the trace buffer if it is to be enabled (0x62) */
1375 if (xscale
->trace
.buffer_enabled
)
1377 if ((retval
= xscale_send_u32(target
, 0x62)) != ERROR_OK
)
1379 if ((retval
= xscale_send_u32(target
, 0x31)) != ERROR_OK
)
1383 if ((retval
= xscale_send_u32(target
, 0x30)) != ERROR_OK
)
1387 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32))) != ERROR_OK
)
1389 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1391 for (i
= 7; i
>= 0; i
--)
1394 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32))) != ERROR_OK
)
1396 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1400 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))) != ERROR_OK
)
1402 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1404 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1406 /* registers are now invalid */
1407 if ((retval
= armv4_5_invalidate_core_regs(target
)) != ERROR_OK
)
1410 /* wait for and process debug entry */
1411 if ((retval
= xscale_debug_entry(target
)) != ERROR_OK
)
1414 LOG_DEBUG("disable single-step");
1415 if ((retval
= xscale_disable_single_step(target
)) != ERROR_OK
)
1418 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1423 static int xscale_step(struct target
*target
, int current
,
1424 uint32_t address
, int handle_breakpoints
)
1426 struct armv4_5_common_s
*armv4_5
= target_to_armv4_5(target
);
1427 struct breakpoint
*breakpoint
= target
->breakpoints
;
1429 uint32_t current_pc
;
1432 if (target
->state
!= TARGET_HALTED
)
1434 LOG_WARNING("target not halted");
1435 return ERROR_TARGET_NOT_HALTED
;
1438 /* current = 1: continue on current pc, otherwise continue at <address> */
1440 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1442 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1444 /* if we're at the reset vector, we have to simulate the step */
1445 if (current_pc
== 0x0)
1447 if ((retval
= arm_simulate_step(target
, NULL
)) != ERROR_OK
)
1449 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1451 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1452 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1457 /* the front-end may request us not to handle breakpoints */
1458 if (handle_breakpoints
)
1459 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1461 if ((retval
= xscale_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1465 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1469 xscale_set_breakpoint(target
, breakpoint
);
1472 LOG_DEBUG("target stepped");
1478 static int xscale_assert_reset(struct target
*target
)
1480 struct xscale_common
*xscale
= target_to_xscale(target
);
1482 LOG_DEBUG("target->state: %s",
1483 target_state_name(target
));
1485 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1486 * end up in T-L-R, which would reset JTAG
1488 jtag_set_end_state(TAP_IDLE
);
1489 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
1491 /* set Hold reset, Halt mode and Trap Reset */
1492 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1493 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1494 xscale_write_dcsr(target
, 1, 0);
1496 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1497 xscale_jtag_set_instr(target
->tap
, 0x7f);
1498 jtag_execute_queue();
1501 jtag_add_reset(0, 1);
1503 /* sleep 1ms, to be sure we fulfill any requirements */
1504 jtag_add_sleep(1000);
1505 jtag_execute_queue();
1507 target
->state
= TARGET_RESET
;
1509 if (target
->reset_halt
)
1512 if ((retval
= target_halt(target
)) != ERROR_OK
)
1519 static int xscale_deassert_reset(struct target
*target
)
1521 struct xscale_common
*xscale
= target_to_xscale(target
);
1522 struct breakpoint
*breakpoint
= target
->breakpoints
;
1526 xscale
->ibcr_available
= 2;
1527 xscale
->ibcr0_used
= 0;
1528 xscale
->ibcr1_used
= 0;
1530 xscale
->dbr_available
= 2;
1531 xscale
->dbr0_used
= 0;
1532 xscale
->dbr1_used
= 0;
1534 /* mark all hardware breakpoints as unset */
1537 if (breakpoint
->type
== BKPT_HARD
)
1539 breakpoint
->set
= 0;
1541 breakpoint
= breakpoint
->next
;
1544 armv4_5_invalidate_core_regs(target
);
1546 /* FIXME mark hardware watchpoints got unset too. Also,
1547 * at least some of the XScale registers are invalid...
1551 * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
1552 * contents got invalidated. Safer to force that, so writing new
1553 * contents can't ever fail..
1558 const uint8_t *buffer
= xscale_debug_handler
;
1562 jtag_add_reset(0, 0);
1564 /* wait 300ms; 150 and 100ms were not enough */
1565 jtag_add_sleep(300*1000);
1567 jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE
));
1568 jtag_execute_queue();
1570 /* set Hold reset, Halt mode and Trap Reset */
1571 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1572 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1573 xscale_write_dcsr(target
, 1, 0);
1575 /* Load the debug handler into the mini-icache. Since
1576 * it's using halt mode (not monitor mode), it runs in
1577 * "Special Debug State" for access to registers, memory,
1578 * coprocessors, trace data, etc.
1580 address
= xscale
->handler_address
;
1581 for (unsigned binary_size
= sizeof xscale_debug_handler
- 1;
1583 binary_size
-= buf_cnt
, buffer
+= buf_cnt
)
1585 uint32_t cache_line
[8];
1588 buf_cnt
= binary_size
;
1592 for (i
= 0; i
< buf_cnt
; i
+= 4)
1594 /* convert LE buffer to host-endian uint32_t */
1595 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1598 for (; i
< 32; i
+= 4)
1600 cache_line
[i
/ 4] = 0xe1a08008;
1603 /* only load addresses other than the reset vectors */
1604 if ((address
% 0x400) != 0x0)
1606 retval
= xscale_load_ic(target
, address
,
1608 if (retval
!= ERROR_OK
)
1615 retval
= xscale_load_ic(target
, 0x0,
1616 xscale
->low_vectors
);
1617 if (retval
!= ERROR_OK
)
1619 retval
= xscale_load_ic(target
, 0xffff0000,
1620 xscale
->high_vectors
);
1621 if (retval
!= ERROR_OK
)
1624 jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE
));
1626 jtag_add_sleep(100000);
1628 /* set Hold reset, Halt mode and Trap Reset */
1629 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1630 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1631 xscale_write_dcsr(target
, 1, 0);
1633 /* clear Hold reset to let the target run (should enter debug handler) */
1634 xscale_write_dcsr(target
, 0, 1);
1635 target
->state
= TARGET_RUNNING
;
1637 if (!target
->reset_halt
)
1639 jtag_add_sleep(10000);
1641 /* we should have entered debug now */
1642 xscale_debug_entry(target
);
1643 target
->state
= TARGET_HALTED
;
1645 /* resume the target */
1646 xscale_resume(target
, 1, 0x0, 1, 0);
1653 static int xscale_read_core_reg(struct target
*target
, int num
,
1654 enum armv4_5_mode mode
)
1656 LOG_ERROR("not implemented");
1660 static int xscale_write_core_reg(struct target
*target
, int num
,
1661 enum armv4_5_mode mode
, uint32_t value
)
1663 LOG_ERROR("not implemented");
1667 static int xscale_full_context(struct target
*target
)
1669 struct armv4_5_common_s
*armv4_5
= target_to_armv4_5(target
);
1677 if (target
->state
!= TARGET_HALTED
)
1679 LOG_WARNING("target not halted");
1680 return ERROR_TARGET_NOT_HALTED
;
1683 buffer
= malloc(4 * 8);
1685 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1686 * we can't enter User mode on an XScale (unpredictable),
1687 * but User shares registers with SYS
1689 for (i
= 1; i
< 7; i
++)
1693 /* check if there are invalid registers in the current mode
1695 for (j
= 0; j
<= 16; j
++)
1697 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1705 /* request banked registers */
1706 xscale_send_u32(target
, 0x0);
1709 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1710 tmp_cpsr
|= 0xc0; /* I/F bits */
1712 /* send CPSR for desired mode */
1713 xscale_send_u32(target
, tmp_cpsr
);
1715 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1716 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1718 xscale_receive(target
, buffer
, 8);
1719 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1720 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1721 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1725 xscale_receive(target
, buffer
, 7);
1728 /* move data from buffer to register cache */
1729 for (j
= 8; j
<= 14; j
++)
1731 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1732 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1733 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1743 static int xscale_restore_context(struct target
*target
)
1745 struct armv4_5_common_s
*armv4_5
= target_to_armv4_5(target
);
1749 if (target
->state
!= TARGET_HALTED
)
1751 LOG_WARNING("target not halted");
1752 return ERROR_TARGET_NOT_HALTED
;
1755 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1756 * we can't enter User mode on an XScale (unpredictable),
1757 * but User shares registers with SYS
1759 for (i
= 1; i
< 7; i
++)
1763 /* check if there are invalid registers in the current mode
1765 for (j
= 8; j
<= 14; j
++)
1767 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1771 /* if not USR/SYS, check if the SPSR needs to be written */
1772 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1774 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1782 /* send banked registers */
1783 xscale_send_u32(target
, 0x1);
1786 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1787 tmp_cpsr
|= 0xc0; /* I/F bits */
1789 /* send CPSR for desired mode */
1790 xscale_send_u32(target
, tmp_cpsr
);
1792 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1793 for (j
= 8; j
<= 14; j
++)
1795 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1796 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1799 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1801 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1802 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1810 static int xscale_read_memory(struct target
*target
, uint32_t address
,
1811 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1813 struct xscale_common
*xscale
= target_to_xscale(target
);
1818 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1820 if (target
->state
!= TARGET_HALTED
)
1822 LOG_WARNING("target not halted");
1823 return ERROR_TARGET_NOT_HALTED
;
1826 /* sanitize arguments */
1827 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1828 return ERROR_INVALID_ARGUMENTS
;
1830 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1831 return ERROR_TARGET_UNALIGNED_ACCESS
;
1833 /* send memory read request (command 0x1n, n: access size) */
1834 if ((retval
= xscale_send_u32(target
, 0x10 | size
)) != ERROR_OK
)
1837 /* send base address for read request */
1838 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1841 /* send number of requested data words */
1842 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1845 /* receive data from target (count times 32-bit words in host endianness) */
1846 buf32
= malloc(4 * count
);
1847 if ((retval
= xscale_receive(target
, buf32
, count
)) != ERROR_OK
)
1850 /* extract data from host-endian buffer into byte stream */
1851 for (i
= 0; i
< count
; i
++)
1856 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1860 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1864 *buffer
++ = buf32
[i
] & 0xff;
1867 LOG_ERROR("invalid read size");
1868 return ERROR_INVALID_ARGUMENTS
;
1874 /* examine DCSR, to see if Sticky Abort (SA) got set */
1875 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1877 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1880 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1883 return ERROR_TARGET_DATA_ABORT
;
1889 static int xscale_write_memory(struct target
*target
, uint32_t address
,
1890 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1892 struct xscale_common
*xscale
= target_to_xscale(target
);
1895 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1897 if (target
->state
!= TARGET_HALTED
)
1899 LOG_WARNING("target not halted");
1900 return ERROR_TARGET_NOT_HALTED
;
1903 /* sanitize arguments */
1904 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1905 return ERROR_INVALID_ARGUMENTS
;
1907 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1908 return ERROR_TARGET_UNALIGNED_ACCESS
;
1910 /* send memory write request (command 0x2n, n: access size) */
1911 if ((retval
= xscale_send_u32(target
, 0x20 | size
)) != ERROR_OK
)
1914 /* send base address for read request */
1915 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1918 /* send number of requested data words to be written*/
1919 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1922 /* extract data from host-endian buffer into byte stream */
1924 for (i
= 0; i
< count
; i
++)
1929 value
= target_buffer_get_u32(target
, buffer
);
1930 xscale_send_u32(target
, value
);
1934 value
= target_buffer_get_u16(target
, buffer
);
1935 xscale_send_u32(target
, value
);
1940 xscale_send_u32(target
, value
);
1944 LOG_ERROR("should never get here");
1949 if ((retval
= xscale_send(target
, buffer
, count
, size
)) != ERROR_OK
)
1952 /* examine DCSR, to see if Sticky Abort (SA) got set */
1953 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1955 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1958 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1961 return ERROR_TARGET_DATA_ABORT
;
1967 static int xscale_bulk_write_memory(struct target
*target
, uint32_t address
,
1968 uint32_t count
, uint8_t *buffer
)
1970 return xscale_write_memory(target
, address
, 4, count
, buffer
);
1973 static uint32_t xscale_get_ttb(struct target
*target
)
1975 struct xscale_common
*xscale
= target_to_xscale(target
);
1978 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
1979 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
1984 static void xscale_disable_mmu_caches(struct target
*target
, int mmu
,
1985 int d_u_cache
, int i_cache
)
1987 struct xscale_common
*xscale
= target_to_xscale(target
);
1988 uint32_t cp15_control
;
1990 /* read cp15 control register */
1991 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1992 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1995 cp15_control
&= ~0x1U
;
2000 xscale_send_u32(target
, 0x50);
2001 xscale_send_u32(target
, xscale
->cache_clean_address
);
2003 /* invalidate DCache */
2004 xscale_send_u32(target
, 0x51);
2006 cp15_control
&= ~0x4U
;
2011 /* invalidate ICache */
2012 xscale_send_u32(target
, 0x52);
2013 cp15_control
&= ~0x1000U
;
2016 /* write new cp15 control register */
2017 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2019 /* execute cpwait to ensure outstanding operations complete */
2020 xscale_send_u32(target
, 0x53);
2023 static void xscale_enable_mmu_caches(struct target
*target
, int mmu
,
2024 int d_u_cache
, int i_cache
)
2026 struct xscale_common
*xscale
= target_to_xscale(target
);
2027 uint32_t cp15_control
;
2029 /* read cp15 control register */
2030 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2031 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2034 cp15_control
|= 0x1U
;
2037 cp15_control
|= 0x4U
;
2040 cp15_control
|= 0x1000U
;
2042 /* write new cp15 control register */
2043 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2045 /* execute cpwait to ensure outstanding operations complete */
2046 xscale_send_u32(target
, 0x53);
2049 static int xscale_set_breakpoint(struct target
*target
,
2050 struct breakpoint
*breakpoint
)
2053 struct xscale_common
*xscale
= target_to_xscale(target
);
2055 if (target
->state
!= TARGET_HALTED
)
2057 LOG_WARNING("target not halted");
2058 return ERROR_TARGET_NOT_HALTED
;
2061 if (breakpoint
->set
)
2063 LOG_WARNING("breakpoint already set");
2067 if (breakpoint
->type
== BKPT_HARD
)
2069 uint32_t value
= breakpoint
->address
| 1;
2070 if (!xscale
->ibcr0_used
)
2072 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2073 xscale
->ibcr0_used
= 1;
2074 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2076 else if (!xscale
->ibcr1_used
)
2078 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2079 xscale
->ibcr1_used
= 1;
2080 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2084 LOG_ERROR("BUG: no hardware comparator available");
2088 else if (breakpoint
->type
== BKPT_SOFT
)
2090 if (breakpoint
->length
== 4)
2092 /* keep the original instruction in target endianness */
2093 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2097 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2098 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
)) != ERROR_OK
)
2105 /* keep the original instruction in target endianness */
2106 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2110 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2111 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
)) != ERROR_OK
)
2116 breakpoint
->set
= 1;
2122 static int xscale_add_breakpoint(struct target
*target
,
2123 struct breakpoint
*breakpoint
)
2125 struct xscale_common
*xscale
= target_to_xscale(target
);
2127 if (target
->state
!= TARGET_HALTED
)
2129 LOG_WARNING("target not halted");
2130 return ERROR_TARGET_NOT_HALTED
;
2133 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2135 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2136 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2139 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2141 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2142 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2145 if (breakpoint
->type
== BKPT_HARD
)
2147 xscale
->ibcr_available
--;
2153 static int xscale_unset_breakpoint(struct target
*target
,
2154 struct breakpoint
*breakpoint
)
2157 struct xscale_common
*xscale
= target_to_xscale(target
);
2159 if (target
->state
!= TARGET_HALTED
)
2161 LOG_WARNING("target not halted");
2162 return ERROR_TARGET_NOT_HALTED
;
2165 if (!breakpoint
->set
)
2167 LOG_WARNING("breakpoint not set");
2171 if (breakpoint
->type
== BKPT_HARD
)
2173 if (breakpoint
->set
== 1)
2175 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2176 xscale
->ibcr0_used
= 0;
2178 else if (breakpoint
->set
== 2)
2180 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2181 xscale
->ibcr1_used
= 0;
2183 breakpoint
->set
= 0;
2187 /* restore original instruction (kept in target endianness) */
2188 if (breakpoint
->length
== 4)
2190 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2197 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2202 breakpoint
->set
= 0;
2208 static int xscale_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
2210 struct xscale_common
*xscale
= target_to_xscale(target
);
2212 if (target
->state
!= TARGET_HALTED
)
2214 LOG_WARNING("target not halted");
2215 return ERROR_TARGET_NOT_HALTED
;
2218 if (breakpoint
->set
)
2220 xscale_unset_breakpoint(target
, breakpoint
);
2223 if (breakpoint
->type
== BKPT_HARD
)
2224 xscale
->ibcr_available
++;
2229 static int xscale_set_watchpoint(struct target
*target
,
2230 struct watchpoint
*watchpoint
)
2232 struct xscale_common
*xscale
= target_to_xscale(target
);
2234 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2235 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2237 if (target
->state
!= TARGET_HALTED
)
2239 LOG_WARNING("target not halted");
2240 return ERROR_TARGET_NOT_HALTED
;
2243 xscale_get_reg(dbcon
);
2245 switch (watchpoint
->rw
)
2257 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2260 if (!xscale
->dbr0_used
)
2262 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2263 dbcon_value
|= enable
;
2264 xscale_set_reg_u32(dbcon
, dbcon_value
);
2265 watchpoint
->set
= 1;
2266 xscale
->dbr0_used
= 1;
2268 else if (!xscale
->dbr1_used
)
2270 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2271 dbcon_value
|= enable
<< 2;
2272 xscale_set_reg_u32(dbcon
, dbcon_value
);
2273 watchpoint
->set
= 2;
2274 xscale
->dbr1_used
= 1;
2278 LOG_ERROR("BUG: no hardware comparator available");
2285 static int xscale_add_watchpoint(struct target
*target
,
2286 struct watchpoint
*watchpoint
)
2288 struct xscale_common
*xscale
= target_to_xscale(target
);
2290 if (target
->state
!= TARGET_HALTED
)
2292 LOG_WARNING("target not halted");
2293 return ERROR_TARGET_NOT_HALTED
;
2296 if (xscale
->dbr_available
< 1)
2298 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2301 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2303 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2306 xscale
->dbr_available
--;
2311 static int xscale_unset_watchpoint(struct target
*target
,
2312 struct watchpoint
*watchpoint
)
2314 struct xscale_common
*xscale
= target_to_xscale(target
);
2315 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2316 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2318 if (target
->state
!= TARGET_HALTED
)
2320 LOG_WARNING("target not halted");
2321 return ERROR_TARGET_NOT_HALTED
;
2324 if (!watchpoint
->set
)
2326 LOG_WARNING("breakpoint not set");
2330 if (watchpoint
->set
== 1)
2332 dbcon_value
&= ~0x3;
2333 xscale_set_reg_u32(dbcon
, dbcon_value
);
2334 xscale
->dbr0_used
= 0;
2336 else if (watchpoint
->set
== 2)
2338 dbcon_value
&= ~0xc;
2339 xscale_set_reg_u32(dbcon
, dbcon_value
);
2340 xscale
->dbr1_used
= 0;
2342 watchpoint
->set
= 0;
2347 static int xscale_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2349 struct xscale_common
*xscale
= target_to_xscale(target
);
2351 if (target
->state
!= TARGET_HALTED
)
2353 LOG_WARNING("target not halted");
2354 return ERROR_TARGET_NOT_HALTED
;
2357 if (watchpoint
->set
)
2359 xscale_unset_watchpoint(target
, watchpoint
);
2362 xscale
->dbr_available
++;
2367 static int xscale_get_reg(struct reg
*reg
)
2369 struct xscale_reg
*arch_info
= reg
->arch_info
;
2370 struct target
*target
= arch_info
->target
;
2371 struct xscale_common
*xscale
= target_to_xscale(target
);
2373 /* DCSR, TX and RX are accessible via JTAG */
2374 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2376 return xscale_read_dcsr(arch_info
->target
);
2378 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2380 /* 1 = consume register content */
2381 return xscale_read_tx(arch_info
->target
, 1);
2383 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2385 /* can't read from RX register (host -> debug handler) */
2388 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2390 /* can't (explicitly) read from TXRXCTRL register */
2393 else /* Other DBG registers have to be transfered by the debug handler */
2395 /* send CP read request (command 0x40) */
2396 xscale_send_u32(target
, 0x40);
2398 /* send CP register number */
2399 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2401 /* read register value */
2402 xscale_read_tx(target
, 1);
2403 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2412 static int xscale_set_reg(struct reg
*reg
, uint8_t* buf
)
2414 struct xscale_reg
*arch_info
= reg
->arch_info
;
2415 struct target
*target
= arch_info
->target
;
2416 struct xscale_common
*xscale
= target_to_xscale(target
);
2417 uint32_t value
= buf_get_u32(buf
, 0, 32);
2419 /* DCSR, TX and RX are accessible via JTAG */
2420 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2422 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2423 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2425 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2427 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2428 return xscale_write_rx(arch_info
->target
);
2430 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2432 /* can't write to TX register (debug-handler -> host) */
2435 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2437 /* can't (explicitly) write to TXRXCTRL register */
2440 else /* Other DBG registers have to be transfered by the debug handler */
2442 /* send CP write request (command 0x41) */
2443 xscale_send_u32(target
, 0x41);
2445 /* send CP register number */
2446 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2448 /* send CP register value */
2449 xscale_send_u32(target
, value
);
2450 buf_set_u32(reg
->value
, 0, 32, value
);
2456 static int xscale_write_dcsr_sw(struct target
*target
, uint32_t value
)
2458 struct xscale_common
*xscale
= target_to_xscale(target
);
2459 struct reg
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2460 struct xscale_reg
*dcsr_arch_info
= dcsr
->arch_info
;
2462 /* send CP write request (command 0x41) */
2463 xscale_send_u32(target
, 0x41);
2465 /* send CP register number */
2466 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2468 /* send CP register value */
2469 xscale_send_u32(target
, value
);
2470 buf_set_u32(dcsr
->value
, 0, 32, value
);
2475 static int xscale_read_trace(struct target
*target
)
2477 struct xscale_common
*xscale
= target_to_xscale(target
);
2478 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
2479 struct xscale_trace_data
**trace_data_p
;
2481 /* 258 words from debug handler
2482 * 256 trace buffer entries
2483 * 2 checkpoint addresses
2485 uint32_t trace_buffer
[258];
2486 int is_address
[256];
2489 if (target
->state
!= TARGET_HALTED
)
2491 LOG_WARNING("target must be stopped to read trace data");
2492 return ERROR_TARGET_NOT_HALTED
;
2495 /* send read trace buffer command (command 0x61) */
2496 xscale_send_u32(target
, 0x61);
2498 /* receive trace buffer content */
2499 xscale_receive(target
, trace_buffer
, 258);
2501 /* parse buffer backwards to identify address entries */
2502 for (i
= 255; i
>= 0; i
--)
2505 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2506 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2509 is_address
[--i
] = 1;
2511 is_address
[--i
] = 1;
2513 is_address
[--i
] = 1;
2515 is_address
[--i
] = 1;
2520 /* search first non-zero entry */
2521 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2526 LOG_DEBUG("no trace data collected");
2527 return ERROR_XSCALE_NO_TRACE_DATA
;
2530 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2533 *trace_data_p
= malloc(sizeof(struct xscale_trace_data
));
2534 (*trace_data_p
)->next
= NULL
;
2535 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2536 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2537 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2538 (*trace_data_p
)->entries
= malloc(sizeof(struct xscale_trace_entry
) * (256 - j
));
2539 (*trace_data_p
)->depth
= 256 - j
;
2541 for (i
= j
; i
< 256; i
++)
2543 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2545 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2547 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2553 static int xscale_read_instruction(struct target
*target
,
2554 struct arm_instruction
*instruction
)
2556 struct xscale_common
*xscale
= target_to_xscale(target
);
2563 if (!xscale
->trace
.image
)
2564 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2566 /* search for the section the current instruction belongs to */
2567 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2569 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2570 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2579 /* current instruction couldn't be found in the image */
2580 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2583 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2586 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2587 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2588 4, buf
, &size_read
)) != ERROR_OK
)
2590 LOG_ERROR("error while reading instruction: %i", retval
);
2591 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2593 opcode
= target_buffer_get_u32(target
, buf
);
2594 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2596 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2599 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2600 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2601 2, buf
, &size_read
)) != ERROR_OK
)
2603 LOG_ERROR("error while reading instruction: %i", retval
);
2604 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2606 opcode
= target_buffer_get_u16(target
, buf
);
2607 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2611 LOG_ERROR("BUG: unknown core state encountered");
2618 static int xscale_branch_address(struct xscale_trace_data
*trace_data
,
2619 int i
, uint32_t *target
)
2621 /* if there are less than four entries prior to the indirect branch message
2622 * we can't extract the address */
2628 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2629 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2634 static int xscale_analyze_trace(struct target
*target
, struct command_context
*cmd_ctx
)
2636 struct xscale_common
*xscale
= target_to_xscale(target
);
2638 uint32_t next_pc
= 0x0;
2639 struct xscale_trace_data
*trace_data
= xscale
->trace
.data
;
2648 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2653 for (i
= 0; i
< trace_data
->depth
; i
++)
2659 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2662 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2664 case 0: /* Exceptions */
2672 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2674 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2675 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2677 case 8: /* Direct Branch */
2680 case 9: /* Indirect Branch */
2682 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2687 case 13: /* Checkpointed Indirect Branch */
2688 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2691 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2692 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2693 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2695 /* explicit fall-through */
2696 case 12: /* Checkpointed Direct Branch */
2701 next_pc
= trace_data
->chkpt0
;
2704 else if (chkpt
== 1)
2707 next_pc
= trace_data
->chkpt0
;
2712 LOG_WARNING("more than two checkpointed branches encountered");
2715 case 15: /* Roll-over */
2718 default: /* Reserved */
2719 command_print(cmd_ctx
, "--- reserved trace message ---");
2720 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2724 if (xscale
->trace
.pc_ok
)
2726 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2727 struct arm_instruction instruction
;
2729 if ((exception
== 6) || (exception
== 7))
2731 /* IRQ or FIQ exception, no instruction executed */
2735 while (executed
-- >= 0)
2737 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2739 /* can't continue tracing with no image available */
2740 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2744 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2746 /* TODO: handle incomplete images */
2750 /* a precise abort on a load to the PC is included in the incremental
2751 * word count, other instructions causing data aborts are not included
2753 if ((executed
== 0) && (exception
== 4)
2754 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2756 if ((instruction
.type
== ARM_LDM
)
2757 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2761 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2762 && (instruction
.info
.load_store
.Rd
!= 15))
2768 /* only the last instruction executed
2769 * (the one that caused the control flow change)
2770 * could be a taken branch
2772 if (((executed
== -1) && (branch
== 1)) &&
2773 (((instruction
.type
== ARM_B
) ||
2774 (instruction
.type
== ARM_BL
) ||
2775 (instruction
.type
== ARM_BLX
)) &&
2776 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff)))
2778 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2782 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2784 command_print(cmd_ctx
, "%s", instruction
.text
);
2792 xscale
->trace
.current_pc
= next_pc
;
2793 xscale
->trace
.pc_ok
= 1;
2797 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2799 struct arm_instruction instruction
;
2800 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2802 /* can't continue tracing with no image available */
2803 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2807 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2809 /* TODO: handle incomplete images */
2812 command_print(cmd_ctx
, "%s", instruction
.text
);
2815 trace_data
= trace_data
->next
;
2821 static const struct reg_arch_type xscale_reg_type
= {
2822 .get
= xscale_get_reg
,
2823 .set
= xscale_set_reg
,
2826 static void xscale_build_reg_cache(struct target
*target
)
2828 struct xscale_common
*xscale
= target_to_xscale(target
);
2829 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
2830 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2831 struct xscale_reg
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2833 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(struct xscale_reg
);
2835 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2836 armv4_5
->core_cache
= (*cache_p
);
2838 (*cache_p
)->next
= malloc(sizeof(struct reg_cache
));
2839 cache_p
= &(*cache_p
)->next
;
2841 /* fill in values for the xscale reg cache */
2842 (*cache_p
)->name
= "XScale registers";
2843 (*cache_p
)->next
= NULL
;
2844 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(struct reg
));
2845 (*cache_p
)->num_regs
= num_regs
;
2847 for (i
= 0; i
< num_regs
; i
++)
2849 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2850 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2851 (*cache_p
)->reg_list
[i
].dirty
= 0;
2852 (*cache_p
)->reg_list
[i
].valid
= 0;
2853 (*cache_p
)->reg_list
[i
].size
= 32;
2854 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2855 (*cache_p
)->reg_list
[i
].type
= &xscale_reg_type
;
2856 arch_info
[i
] = xscale_reg_arch_info
[i
];
2857 arch_info
[i
].target
= target
;
2860 xscale
->reg_cache
= (*cache_p
);
2863 static int xscale_init_target(struct command_context
*cmd_ctx
,
2864 struct target
*target
)
2866 xscale_build_reg_cache(target
);
2870 static int xscale_init_arch_info(struct target
*target
,
2871 struct xscale_common
*xscale
, struct jtag_tap
*tap
, const char *variant
)
2873 struct arm
*armv4_5
;
2874 uint32_t high_reset_branch
, low_reset_branch
;
2877 armv4_5
= &xscale
->armv4_5_common
;
2879 /* store architecture specfic data (none so far) */
2880 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
2882 /* we don't really *need* variant info ... */
2886 if (strcmp(variant
, "pxa250") == 0
2887 || strcmp(variant
, "pxa255") == 0
2888 || strcmp(variant
, "pxa26x") == 0)
2890 else if (strcmp(variant
, "pxa27x") == 0
2891 || strcmp(variant
, "ixp42x") == 0
2892 || strcmp(variant
, "ixp45x") == 0
2893 || strcmp(variant
, "ixp46x") == 0)
2896 LOG_WARNING("%s: unrecognized variant %s",
2897 tap
->dotted_name
, variant
);
2899 if (ir_length
&& ir_length
!= tap
->ir_length
) {
2900 LOG_WARNING("%s: IR length for %s is %d; fixing",
2901 tap
->dotted_name
, variant
, ir_length
);
2902 tap
->ir_length
= ir_length
;
2906 /* the debug handler isn't installed (and thus not running) at this time */
2907 xscale
->handler_address
= 0xfe000800;
2909 /* clear the vectors we keep locally for reference */
2910 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
2911 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
2913 /* no user-specified vectors have been configured yet */
2914 xscale
->static_low_vectors_set
= 0x0;
2915 xscale
->static_high_vectors_set
= 0x0;
2917 /* calculate branches to debug handler */
2918 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
2919 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
2921 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
2922 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
2924 for (i
= 1; i
<= 7; i
++)
2926 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2927 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2930 /* 64kB aligned region used for DCache cleaning */
2931 xscale
->cache_clean_address
= 0xfffe0000;
2933 xscale
->hold_rst
= 0;
2934 xscale
->external_debug_break
= 0;
2936 xscale
->ibcr_available
= 2;
2937 xscale
->ibcr0_used
= 0;
2938 xscale
->ibcr1_used
= 0;
2940 xscale
->dbr_available
= 2;
2941 xscale
->dbr0_used
= 0;
2942 xscale
->dbr1_used
= 0;
2944 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
2945 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
2947 xscale
->vector_catch
= 0x1;
2949 xscale
->trace
.capture_status
= TRACE_IDLE
;
2950 xscale
->trace
.data
= NULL
;
2951 xscale
->trace
.image
= NULL
;
2952 xscale
->trace
.buffer_enabled
= 0;
2953 xscale
->trace
.buffer_fill
= 0;
2955 /* prepare ARMv4/5 specific information */
2956 armv4_5
->arch_info
= xscale
;
2957 armv4_5
->read_core_reg
= xscale_read_core_reg
;
2958 armv4_5
->write_core_reg
= xscale_write_core_reg
;
2959 armv4_5
->full_context
= xscale_full_context
;
2961 armv4_5_init_arch_info(target
, armv4_5
);
2963 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
2964 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
2965 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
2966 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
2967 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
2968 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
2969 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
2970 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
2975 static int xscale_target_create(struct target
*target
, Jim_Interp
*interp
)
2977 struct xscale_common
*xscale
;
2979 if (sizeof xscale_debug_handler
- 1 > 0x800) {
2980 LOG_ERROR("debug_handler.bin: larger than 2kb");
2984 xscale
= calloc(1, sizeof(*xscale
));
2988 return xscale_init_arch_info(target
, xscale
, target
->tap
,
2992 COMMAND_HANDLER(xscale_handle_debug_handler_command
)
2994 struct target
*target
= NULL
;
2995 struct xscale_common
*xscale
;
2997 uint32_t handler_address
;
3001 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3005 if ((target
= get_target(CMD_ARGV
[0])) == NULL
)
3007 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3011 xscale
= target_to_xscale(target
);
3012 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3013 if (retval
!= ERROR_OK
)
3016 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], handler_address
);
3018 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3019 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3021 xscale
->handler_address
= handler_address
;
3025 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3032 COMMAND_HANDLER(xscale_handle_cache_clean_address_command
)
3034 struct target
*target
= NULL
;
3035 struct xscale_common
*xscale
;
3037 uint32_t cache_clean_address
;
3041 return ERROR_COMMAND_SYNTAX_ERROR
;
3044 target
= get_target(CMD_ARGV
[0]);
3047 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3050 xscale
= target_to_xscale(target
);
3051 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3052 if (retval
!= ERROR_OK
)
3055 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cache_clean_address
);
3057 if (cache_clean_address
& 0xffff)
3059 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3063 xscale
->cache_clean_address
= cache_clean_address
;
3069 COMMAND_HANDLER(xscale_handle_cache_info_command
)
3071 struct target
*target
= get_current_target(CMD_CTX
);
3072 struct xscale_common
*xscale
= target_to_xscale(target
);
3075 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3076 if (retval
!= ERROR_OK
)
3079 return armv4_5_handle_cache_info_command(CMD_CTX
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3082 static int xscale_virt2phys(struct target
*target
,
3083 uint32_t virtual, uint32_t *physical
)
3085 struct xscale_common
*xscale
= target_to_xscale(target
);
3091 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
3092 LOG_ERROR(xscale_not
);
3093 return ERROR_TARGET_INVALID
;
3096 uint32_t ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3105 static int xscale_mmu(struct target
*target
, int *enabled
)
3107 struct xscale_common
*xscale
= target_to_xscale(target
);
3109 if (target
->state
!= TARGET_HALTED
)
3111 LOG_ERROR("Target not halted");
3112 return ERROR_TARGET_INVALID
;
3114 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3118 COMMAND_HANDLER(xscale_handle_mmu_command
)
3120 struct target
*target
= get_current_target(CMD_CTX
);
3121 struct xscale_common
*xscale
= target_to_xscale(target
);
3124 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3125 if (retval
!= ERROR_OK
)
3128 if (target
->state
!= TARGET_HALTED
)
3130 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3136 if (strcmp("enable", CMD_ARGV
[0]) == 0)
3138 xscale_enable_mmu_caches(target
, 1, 0, 0);
3139 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3141 else if (strcmp("disable", CMD_ARGV
[0]) == 0)
3143 xscale_disable_mmu_caches(target
, 1, 0, 0);
3144 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3148 command_print(CMD_CTX
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3153 COMMAND_HANDLER(xscale_handle_idcache_command
)
3155 struct target
*target
= get_current_target(CMD_CTX
);
3156 struct xscale_common
*xscale
= target_to_xscale(target
);
3157 int icache
= 0, dcache
= 0;
3160 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3161 if (retval
!= ERROR_OK
)
3164 if (target
->state
!= TARGET_HALTED
)
3166 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3170 if (strcmp(CMD_NAME
, "icache") == 0)
3172 else if (strcmp(CMD_NAME
, "dcache") == 0)
3177 if (strcmp("enable", CMD_ARGV
[0]) == 0)
3179 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3182 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3184 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3186 else if (strcmp("disable", CMD_ARGV
[0]) == 0)
3188 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3191 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3193 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3198 command_print(CMD_CTX
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3201 command_print(CMD_CTX
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3206 COMMAND_HANDLER(xscale_handle_vector_catch_command
)
3208 struct target
*target
= get_current_target(CMD_CTX
);
3209 struct xscale_common
*xscale
= target_to_xscale(target
);
3212 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3213 if (retval
!= ERROR_OK
)
3218 command_print(CMD_CTX
, "usage: xscale vector_catch [mask]");
3222 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[0], xscale
->vector_catch
);
3223 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3224 xscale_write_dcsr(target
, -1, -1);
3227 command_print(CMD_CTX
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3233 COMMAND_HANDLER(xscale_handle_vector_table_command
)
3235 struct target
*target
= get_current_target(CMD_CTX
);
3236 struct xscale_common
*xscale
= target_to_xscale(target
);
3240 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3241 if (retval
!= ERROR_OK
)
3244 if (CMD_ARGC
== 0) /* print current settings */
3248 command_print(CMD_CTX
, "active user-set static vectors:");
3249 for (idx
= 1; idx
< 8; idx
++)
3250 if (xscale
->static_low_vectors_set
& (1 << idx
))
3251 command_print(CMD_CTX
, "low %d: 0x%" PRIx32
, idx
, xscale
->static_low_vectors
[idx
]);
3252 for (idx
= 1; idx
< 8; idx
++)
3253 if (xscale
->static_high_vectors_set
& (1 << idx
))
3254 command_print(CMD_CTX
, "high %d: 0x%" PRIx32
, idx
, xscale
->static_high_vectors
[idx
]);
3263 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], idx
);
3265 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], vec
);
3267 if (idx
< 1 || idx
>= 8)
3270 if (!err
&& strcmp(CMD_ARGV
[0], "low") == 0)
3272 xscale
->static_low_vectors_set
|= (1<<idx
);
3273 xscale
->static_low_vectors
[idx
] = vec
;
3275 else if (!err
&& (strcmp(CMD_ARGV
[0], "high") == 0))
3277 xscale
->static_high_vectors_set
|= (1<<idx
);
3278 xscale
->static_high_vectors
[idx
] = vec
;
3285 command_print(CMD_CTX
, "usage: xscale vector_table <high|low> <index> <code>");
3291 COMMAND_HANDLER(xscale_handle_trace_buffer_command
)
3293 struct target
*target
= get_current_target(CMD_CTX
);
3294 struct xscale_common
*xscale
= target_to_xscale(target
);
3295 struct armv4_5_common_s
*armv4_5
= &xscale
->armv4_5_common
;
3296 uint32_t dcsr_value
;
3299 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3300 if (retval
!= ERROR_OK
)
3303 if (target
->state
!= TARGET_HALTED
)
3305 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3309 if ((CMD_ARGC
>= 1) && (strcmp("enable", CMD_ARGV
[0]) == 0))
3311 struct xscale_trace_data
*td
, *next_td
;
3312 xscale
->trace
.buffer_enabled
= 1;
3314 /* free old trace data */
3315 td
= xscale
->trace
.data
;
3325 xscale
->trace
.data
= NULL
;
3327 else if ((CMD_ARGC
>= 1) && (strcmp("disable", CMD_ARGV
[0]) == 0))
3329 xscale
->trace
.buffer_enabled
= 0;
3332 if ((CMD_ARGC
>= 2) && (strcmp("fill", CMD_ARGV
[1]) == 0))
3336 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], fill
);
3337 xscale
->trace
.buffer_fill
= fill
;
3339 else if ((CMD_ARGC
>= 2) && (strcmp("wrap", CMD_ARGV
[1]) == 0))
3341 xscale
->trace
.buffer_fill
= -1;
3344 if (xscale
->trace
.buffer_enabled
)
3346 /* if we enable the trace buffer in fill-once
3347 * mode we know the address of the first instruction */
3348 xscale
->trace
.pc_ok
= 1;
3349 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3353 /* otherwise the address is unknown, and we have no known good PC */
3354 xscale
->trace
.pc_ok
= 0;
3357 command_print(CMD_CTX
, "trace buffer %s (%s)",
3358 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3359 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3361 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3362 if (xscale
->trace
.buffer_fill
>= 0)
3363 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3365 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3370 COMMAND_HANDLER(xscale_handle_trace_image_command
)
3372 struct target
*target
= get_current_target(CMD_CTX
);
3373 struct xscale_common
*xscale
= target_to_xscale(target
);
3378 command_print(CMD_CTX
, "usage: xscale trace_image <file> [base address] [type]");
3382 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3383 if (retval
!= ERROR_OK
)
3386 if (xscale
->trace
.image
)
3388 image_close(xscale
->trace
.image
);
3389 free(xscale
->trace
.image
);
3390 command_print(CMD_CTX
, "previously loaded image found and closed");
3393 xscale
->trace
.image
= malloc(sizeof(struct image
));
3394 xscale
->trace
.image
->base_address_set
= 0;
3395 xscale
->trace
.image
->start_address_set
= 0;
3397 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3400 xscale
->trace
.image
->base_address_set
= 1;
3401 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], xscale
->trace
.image
->base_address
);
3405 xscale
->trace
.image
->base_address_set
= 0;
3408 if (image_open(xscale
->trace
.image
, CMD_ARGV
[0], (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
)
3410 free(xscale
->trace
.image
);
3411 xscale
->trace
.image
= NULL
;
3418 COMMAND_HANDLER(xscale_handle_dump_trace_command
)
3420 struct target
*target
= get_current_target(CMD_CTX
);
3421 struct xscale_common
*xscale
= target_to_xscale(target
);
3422 struct xscale_trace_data
*trace_data
;
3426 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3427 if (retval
!= ERROR_OK
)
3430 if (target
->state
!= TARGET_HALTED
)
3432 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3438 command_print(CMD_CTX
, "usage: xscale dump_trace <file>");
3442 trace_data
= xscale
->trace
.data
;
3446 command_print(CMD_CTX
, "no trace data collected");
3450 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3459 fileio_write_u32(&file
, trace_data
->chkpt0
);
3460 fileio_write_u32(&file
, trace_data
->chkpt1
);
3461 fileio_write_u32(&file
, trace_data
->last_instruction
);
3462 fileio_write_u32(&file
, trace_data
->depth
);
3464 for (i
= 0; i
< trace_data
->depth
; i
++)
3465 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3467 trace_data
= trace_data
->next
;
3470 fileio_close(&file
);
3475 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command
)
3477 struct target
*target
= get_current_target(CMD_CTX
);
3478 struct xscale_common
*xscale
= target_to_xscale(target
);
3481 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3482 if (retval
!= ERROR_OK
)
3485 xscale_analyze_trace(target
, CMD_CTX
);
3490 COMMAND_HANDLER(xscale_handle_cp15
)
3492 struct target
*target
= get_current_target(CMD_CTX
);
3493 struct xscale_common
*xscale
= target_to_xscale(target
);
3496 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3497 if (retval
!= ERROR_OK
)
3500 if (target
->state
!= TARGET_HALTED
)
3502 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3505 uint32_t reg_no
= 0;
3506 struct reg
*reg
= NULL
;
3509 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg_no
);
3510 /*translate from xscale cp15 register no to openocd register*/
3514 reg_no
= XSCALE_MAINID
;
3517 reg_no
= XSCALE_CTRL
;
3520 reg_no
= XSCALE_TTB
;
3523 reg_no
= XSCALE_DAC
;
3526 reg_no
= XSCALE_FSR
;
3529 reg_no
= XSCALE_FAR
;
3532 reg_no
= XSCALE_PID
;
3535 reg_no
= XSCALE_CPACCESS
;
3538 command_print(CMD_CTX
, "invalid register number");
3539 return ERROR_INVALID_ARGUMENTS
;
3541 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3548 /* read cp15 control register */
3549 xscale_get_reg(reg
);
3550 value
= buf_get_u32(reg
->value
, 0, 32);
3551 command_print(CMD_CTX
, "%s (/%i): 0x%" PRIx32
"", reg
->name
, (int)(reg
->size
), value
);
3553 else if (CMD_ARGC
== 2)
3556 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
3558 /* send CP write request (command 0x41) */
3559 xscale_send_u32(target
, 0x41);
3561 /* send CP register number */
3562 xscale_send_u32(target
, reg_no
);
3564 /* send CP register value */
3565 xscale_send_u32(target
, value
);
3567 /* execute cpwait to ensure outstanding operations complete */
3568 xscale_send_u32(target
, 0x53);
3572 command_print(CMD_CTX
, "usage: cp15 [register]<, [value]>");
3578 static int xscale_register_commands(struct command_context
*cmd_ctx
)
3580 struct command
*xscale_cmd
;
3582 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3584 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3585 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3587 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3588 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3589 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3590 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3592 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_vector_catch_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3593 register_command(cmd_ctx
, xscale_cmd
, "vector_table", xscale_handle_vector_table_command
, COMMAND_EXEC
, "<high|low> <index> <code> set static code for exception handler entry");
3595 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable | disable> ['fill' [n]|'wrap']");
3597 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3598 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3599 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3600 COMMAND_EXEC
, "load image from <file> [base address]");
3602 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3604 armv4_5_register_commands(cmd_ctx
);
3609 struct target_type xscale_target
=
3613 .poll
= xscale_poll
,
3614 .arch_state
= xscale_arch_state
,
3616 .target_request_data
= NULL
,
3618 .halt
= xscale_halt
,
3619 .resume
= xscale_resume
,
3620 .step
= xscale_step
,
3622 .assert_reset
= xscale_assert_reset
,
3623 .deassert_reset
= xscale_deassert_reset
,
3624 .soft_reset_halt
= NULL
,
3626 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
3628 .read_memory
= xscale_read_memory
,
3629 .write_memory
= xscale_write_memory
,
3630 .bulk_write_memory
= xscale_bulk_write_memory
,
3632 .checksum_memory
= arm_checksum_memory
,
3633 .blank_check_memory
= arm_blank_check_memory
,
3635 .run_algorithm
= armv4_5_run_algorithm
,
3637 .add_breakpoint
= xscale_add_breakpoint
,
3638 .remove_breakpoint
= xscale_remove_breakpoint
,
3639 .add_watchpoint
= xscale_add_watchpoint
,
3640 .remove_watchpoint
= xscale_remove_watchpoint
,
3642 .register_commands
= xscale_register_commands
,
3643 .target_create
= xscale_target_create
,
3644 .init_target
= xscale_init_target
,
3646 .virt2phys
= xscale_virt2phys
,
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