1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include "target_type.h"
32 #include "arm7_9_common.h"
33 #include "arm_simulator.h"
34 #include "arm_disassembler.h"
35 #include "time_support.h"
39 int xscale_register_commands(struct command_context_s
*cmd_ctx
);
41 /* forward declarations */
42 int xscale_target_create(struct target_s
*target
, Jim_Interp
*interp
);
43 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
44 int xscale_quit(void);
46 int xscale_arch_state(struct target_s
*target
);
47 int xscale_poll(target_t
*target
);
48 int xscale_halt(target_t
*target
);
49 int xscale_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
);
50 int xscale_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
);
51 int xscale_debug_entry(target_t
*target
);
52 int xscale_restore_context(target_t
*target
);
54 int xscale_assert_reset(target_t
*target
);
55 int xscale_deassert_reset(target_t
*target
);
56 int xscale_soft_reset_halt(struct target_s
*target
);
58 int xscale_set_reg_u32(reg_t
*reg
, uint32_t value
);
60 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
61 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, uint32_t value
);
63 int xscale_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
64 int xscale_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
65 int xscale_bulk_write_memory(target_t
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
);
67 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
68 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
69 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
70 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
71 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
72 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
73 void xscale_enable_watchpoints(struct target_s
*target
);
74 void xscale_enable_breakpoints(struct target_s
*target
);
75 static int xscale_virt2phys(struct target_s
*target
, uint32_t virtual, uint32_t *physical
);
76 static int xscale_mmu(struct target_s
*target
, int *enabled
);
78 int xscale_read_trace(target_t
*target
);
80 target_type_t xscale_target
=
85 .arch_state
= xscale_arch_state
,
87 .target_request_data
= NULL
,
90 .resume
= xscale_resume
,
93 .assert_reset
= xscale_assert_reset
,
94 .deassert_reset
= xscale_deassert_reset
,
95 .soft_reset_halt
= xscale_soft_reset_halt
,
97 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
99 .read_memory
= xscale_read_memory
,
100 .write_memory
= xscale_write_memory
,
101 .bulk_write_memory
= xscale_bulk_write_memory
,
102 .checksum_memory
= arm7_9_checksum_memory
,
103 .blank_check_memory
= arm7_9_blank_check_memory
,
105 .run_algorithm
= armv4_5_run_algorithm
,
107 .add_breakpoint
= xscale_add_breakpoint
,
108 .remove_breakpoint
= xscale_remove_breakpoint
,
109 .add_watchpoint
= xscale_add_watchpoint
,
110 .remove_watchpoint
= xscale_remove_watchpoint
,
112 .register_commands
= xscale_register_commands
,
113 .target_create
= xscale_target_create
,
114 .init_target
= xscale_init_target
,
117 .virt2phys
= xscale_virt2phys
,
121 char* xscale_reg_list
[] =
123 "XSCALE_MAINID", /* 0 */
133 "XSCALE_IBCR0", /* 10 */
143 "XSCALE_RX", /* 20 */
147 xscale_reg_t xscale_reg_arch_info
[] =
149 {XSCALE_MAINID
, NULL
},
150 {XSCALE_CACHETYPE
, NULL
},
152 {XSCALE_AUXCTRL
, NULL
},
158 {XSCALE_CPACCESS
, NULL
},
159 {XSCALE_IBCR0
, NULL
},
160 {XSCALE_IBCR1
, NULL
},
163 {XSCALE_DBCON
, NULL
},
164 {XSCALE_TBREG
, NULL
},
165 {XSCALE_CHKPT0
, NULL
},
166 {XSCALE_CHKPT1
, NULL
},
167 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
168 {-1, NULL
}, /* TX accessed via JTAG */
169 {-1, NULL
}, /* RX accessed via JTAG */
170 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
173 int xscale_reg_arch_type
= -1;
175 int xscale_get_reg(reg_t
*reg
);
176 int xscale_set_reg(reg_t
*reg
, uint8_t *buf
);
178 int xscale_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
180 armv4_5_common_t
*armv4_5
= target
->arch_info
;
181 xscale_common_t
*xscale
= armv4_5
->arch_info
;
183 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
185 LOG_ERROR("target isn't an XScale target");
189 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
191 LOG_ERROR("target isn't an XScale target");
195 *armv4_5_p
= armv4_5
;
201 int xscale_jtag_set_instr(jtag_tap_t
*tap
, uint32_t new_instr
)
206 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
211 field
.num_bits
= tap
->ir_length
;
212 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
213 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
216 field
.in_value
= tmp
;
218 jtag_add_ir_scan(1, &field
, jtag_get_end_state());
220 /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
221 jtag_check_value_mask(&field
, tap
->expected
, tap
->expected_mask
);
223 free(field
.out_value
);
229 int xscale_read_dcsr(target_t
*target
)
231 armv4_5_common_t
*armv4_5
= target
->arch_info
;
232 xscale_common_t
*xscale
= armv4_5
->arch_info
;
236 scan_field_t fields
[3];
237 uint8_t field0
= 0x0;
238 uint8_t field0_check_value
= 0x2;
239 uint8_t field0_check_mask
= 0x7;
240 uint8_t field2
= 0x0;
241 uint8_t field2_check_value
= 0x0;
242 uint8_t field2_check_mask
= 0x1;
244 jtag_set_end_state(TAP_DRPAUSE
);
245 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
247 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
248 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
250 fields
[0].tap
= xscale
->jtag_info
.tap
;
251 fields
[0].num_bits
= 3;
252 fields
[0].out_value
= &field0
;
254 fields
[0].in_value
= &tmp
;
256 fields
[1].tap
= xscale
->jtag_info
.tap
;
257 fields
[1].num_bits
= 32;
258 fields
[1].out_value
= NULL
;
259 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
262 fields
[2].tap
= xscale
->jtag_info
.tap
;
263 fields
[2].num_bits
= 1;
264 fields
[2].out_value
= &field2
;
266 fields
[2].in_value
= &tmp2
;
268 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
270 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
271 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
273 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
275 LOG_ERROR("JTAG error while reading DCSR");
279 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
280 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
282 /* write the register with the value we just read
283 * on this second pass, only the first bit of field0 is guaranteed to be 0)
285 field0_check_mask
= 0x1;
286 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
287 fields
[1].in_value
= NULL
;
289 jtag_set_end_state(TAP_IDLE
);
291 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
293 /* DANGER!!! this must be here. It will make sure that the arguments
294 * to jtag_set_check_value() does not go out of scope! */
295 return jtag_execute_queue();
299 static void xscale_getbuf(jtag_callback_data_t arg
)
301 uint8_t *in
= (uint8_t *)arg
;
302 *((uint32_t *)in
) = buf_get_u32(in
, 0, 32);
305 int xscale_receive(target_t
*target
, uint32_t *buffer
, int num_words
)
308 return ERROR_INVALID_ARGUMENTS
;
310 int retval
= ERROR_OK
;
311 armv4_5_common_t
*armv4_5
= target
->arch_info
;
312 xscale_common_t
*xscale
= armv4_5
->arch_info
;
315 scan_field_t fields
[3];
317 uint8_t *field0
= malloc(num_words
* 1);
318 uint8_t field0_check_value
= 0x2;
319 uint8_t field0_check_mask
= 0x6;
320 uint32_t *field1
= malloc(num_words
* 4);
321 uint8_t field2_check_value
= 0x0;
322 uint8_t field2_check_mask
= 0x1;
324 int words_scheduled
= 0;
328 path
[0] = TAP_DRSELECT
;
329 path
[1] = TAP_DRCAPTURE
;
330 path
[2] = TAP_DRSHIFT
;
332 fields
[0].tap
= xscale
->jtag_info
.tap
;
333 fields
[0].num_bits
= 3;
334 fields
[0].out_value
= NULL
;
335 fields
[0].in_value
= NULL
;
336 fields
[0].check_value
= &field0_check_value
;
337 fields
[0].check_mask
= &field0_check_mask
;
339 fields
[1].tap
= xscale
->jtag_info
.tap
;
340 fields
[1].num_bits
= 32;
341 fields
[1].out_value
= NULL
;
342 fields
[1].check_value
= NULL
;
343 fields
[1].check_mask
= NULL
;
345 fields
[2].tap
= xscale
->jtag_info
.tap
;
346 fields
[2].num_bits
= 1;
347 fields
[2].out_value
= NULL
;
348 fields
[2].in_value
= NULL
;
349 fields
[2].check_value
= &field2_check_value
;
350 fields
[2].check_mask
= &field2_check_mask
;
352 jtag_set_end_state(TAP_IDLE
);
353 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgtx
);
354 jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
356 /* repeat until all words have been collected */
358 while (words_done
< num_words
)
362 for (i
= words_done
; i
< num_words
; i
++)
364 fields
[0].in_value
= &field0
[i
];
366 jtag_add_pathmove(3, path
);
368 fields
[1].in_value
= (uint8_t *)(field1
+ i
);
370 jtag_add_dr_scan_check(3, fields
, jtag_set_end_state(TAP_IDLE
));
372 jtag_add_callback(xscale_getbuf
, (jtag_callback_data_t
)(field1
+ i
));
377 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
379 LOG_ERROR("JTAG error while receiving data from debug handler");
383 /* examine results */
384 for (i
= words_done
; i
< num_words
; i
++)
386 if (!(field0
[0] & 1))
388 /* move backwards if necessary */
390 for (j
= i
; j
< num_words
- 1; j
++)
392 field0
[j
] = field0
[j
+ 1];
393 field1
[j
] = field1
[j
+ 1];
398 if (words_scheduled
== 0)
400 if (attempts
++==1000)
402 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
403 retval
= ERROR_TARGET_TIMEOUT
;
408 words_done
+= words_scheduled
;
411 for (i
= 0; i
< num_words
; i
++)
412 *(buffer
++) = buf_get_u32((uint8_t*)&field1
[i
], 0, 32);
419 int xscale_read_tx(target_t
*target
, int consume
)
421 armv4_5_common_t
*armv4_5
= target
->arch_info
;
422 xscale_common_t
*xscale
= armv4_5
->arch_info
;
424 tap_state_t noconsume_path
[6];
427 struct timeval timeout
, now
;
429 scan_field_t fields
[3];
430 uint8_t field0_in
= 0x0;
431 uint8_t field0_check_value
= 0x2;
432 uint8_t field0_check_mask
= 0x6;
433 uint8_t field2_check_value
= 0x0;
434 uint8_t field2_check_mask
= 0x1;
436 jtag_set_end_state(TAP_IDLE
);
438 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgtx
);
440 path
[0] = TAP_DRSELECT
;
441 path
[1] = TAP_DRCAPTURE
;
442 path
[2] = TAP_DRSHIFT
;
444 noconsume_path
[0] = TAP_DRSELECT
;
445 noconsume_path
[1] = TAP_DRCAPTURE
;
446 noconsume_path
[2] = TAP_DREXIT1
;
447 noconsume_path
[3] = TAP_DRPAUSE
;
448 noconsume_path
[4] = TAP_DREXIT2
;
449 noconsume_path
[5] = TAP_DRSHIFT
;
451 fields
[0].tap
= xscale
->jtag_info
.tap
;
452 fields
[0].num_bits
= 3;
453 fields
[0].out_value
= NULL
;
454 fields
[0].in_value
= &field0_in
;
456 fields
[1].tap
= xscale
->jtag_info
.tap
;
457 fields
[1].num_bits
= 32;
458 fields
[1].out_value
= NULL
;
459 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
462 fields
[2].tap
= xscale
->jtag_info
.tap
;
463 fields
[2].num_bits
= 1;
464 fields
[2].out_value
= NULL
;
466 fields
[2].in_value
= &tmp
;
468 gettimeofday(&timeout
, NULL
);
469 timeval_add_time(&timeout
, 1, 0);
473 /* if we want to consume the register content (i.e. clear TX_READY),
474 * we have to go straight from Capture-DR to Shift-DR
475 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
478 jtag_add_pathmove(3, path
);
481 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
484 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
486 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
487 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
489 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
491 LOG_ERROR("JTAG error while reading TX");
492 return ERROR_TARGET_TIMEOUT
;
495 gettimeofday(&now
, NULL
);
496 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
498 LOG_ERROR("time out reading TX register");
499 return ERROR_TARGET_TIMEOUT
;
501 if (!((!(field0_in
& 1)) && consume
))
505 if (debug_level
>= 3)
507 LOG_DEBUG("waiting 100ms");
508 alive_sleep(100); /* avoid flooding the logs */
516 if (!(field0_in
& 1))
517 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
522 int xscale_write_rx(target_t
*target
)
524 armv4_5_common_t
*armv4_5
= target
->arch_info
;
525 xscale_common_t
*xscale
= armv4_5
->arch_info
;
528 struct timeval timeout
, now
;
530 scan_field_t fields
[3];
531 uint8_t field0_out
= 0x0;
532 uint8_t field0_in
= 0x0;
533 uint8_t field0_check_value
= 0x2;
534 uint8_t field0_check_mask
= 0x6;
535 uint8_t field2
= 0x0;
536 uint8_t field2_check_value
= 0x0;
537 uint8_t field2_check_mask
= 0x1;
539 jtag_set_end_state(TAP_IDLE
);
541 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgrx
);
543 fields
[0].tap
= xscale
->jtag_info
.tap
;
544 fields
[0].num_bits
= 3;
545 fields
[0].out_value
= &field0_out
;
546 fields
[0].in_value
= &field0_in
;
548 fields
[1].tap
= xscale
->jtag_info
.tap
;
549 fields
[1].num_bits
= 32;
550 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
551 fields
[1].in_value
= NULL
;
554 fields
[2].tap
= xscale
->jtag_info
.tap
;
555 fields
[2].num_bits
= 1;
556 fields
[2].out_value
= &field2
;
558 fields
[2].in_value
= &tmp
;
560 gettimeofday(&timeout
, NULL
);
561 timeval_add_time(&timeout
, 1, 0);
563 /* poll until rx_read is low */
564 LOG_DEBUG("polling RX");
567 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
569 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
570 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
572 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
574 LOG_ERROR("JTAG error while writing RX");
578 gettimeofday(&now
, NULL
);
579 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
581 LOG_ERROR("time out writing RX register");
582 return ERROR_TARGET_TIMEOUT
;
584 if (!(field0_in
& 1))
586 if (debug_level
>= 3)
588 LOG_DEBUG("waiting 100ms");
589 alive_sleep(100); /* avoid flooding the logs */
599 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
601 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
603 LOG_ERROR("JTAG error while writing RX");
610 /* send count elements of size byte to the debug handler */
611 int xscale_send(target_t
*target
, uint8_t *buffer
, int count
, int size
)
613 armv4_5_common_t
*armv4_5
= target
->arch_info
;
614 xscale_common_t
*xscale
= armv4_5
->arch_info
;
622 jtag_set_end_state(TAP_IDLE
);
624 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dbgrx
);
631 int endianness
= target
->endianness
;
632 while (done_count
++ < count
)
637 if (endianness
== TARGET_LITTLE_ENDIAN
)
639 t
[1]=le_to_h_u32(buffer
);
642 t
[1]=be_to_h_u32(buffer
);
646 if (endianness
== TARGET_LITTLE_ENDIAN
)
648 t
[1]=le_to_h_u16(buffer
);
651 t
[1]=be_to_h_u16(buffer
);
658 LOG_ERROR("BUG: size neither 4, 2 nor 1");
661 jtag_add_dr_out(xscale
->jtag_info
.tap
,
665 jtag_set_end_state(TAP_IDLE
));
669 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
671 LOG_ERROR("JTAG error while sending data to debug handler");
678 int xscale_send_u32(target_t
*target
, uint32_t value
)
680 armv4_5_common_t
*armv4_5
= target
->arch_info
;
681 xscale_common_t
*xscale
= armv4_5
->arch_info
;
683 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
684 return xscale_write_rx(target
);
687 int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
689 armv4_5_common_t
*armv4_5
= target
->arch_info
;
690 xscale_common_t
*xscale
= armv4_5
->arch_info
;
694 scan_field_t fields
[3];
695 uint8_t field0
= 0x0;
696 uint8_t field0_check_value
= 0x2;
697 uint8_t field0_check_mask
= 0x7;
698 uint8_t field2
= 0x0;
699 uint8_t field2_check_value
= 0x0;
700 uint8_t field2_check_mask
= 0x1;
703 xscale
->hold_rst
= hold_rst
;
705 if (ext_dbg_brk
!= -1)
706 xscale
->external_debug_break
= ext_dbg_brk
;
708 jtag_set_end_state(TAP_IDLE
);
709 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
711 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
712 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
714 fields
[0].tap
= xscale
->jtag_info
.tap
;
715 fields
[0].num_bits
= 3;
716 fields
[0].out_value
= &field0
;
718 fields
[0].in_value
= &tmp
;
720 fields
[1].tap
= xscale
->jtag_info
.tap
;
721 fields
[1].num_bits
= 32;
722 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
723 fields
[1].in_value
= NULL
;
726 fields
[2].tap
= xscale
->jtag_info
.tap
;
727 fields
[2].num_bits
= 1;
728 fields
[2].out_value
= &field2
;
730 fields
[2].in_value
= &tmp2
;
732 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
734 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
735 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
737 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
739 LOG_ERROR("JTAG error while writing DCSR");
743 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
744 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
749 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
750 unsigned int parity (unsigned int v
)
757 LOG_DEBUG("parity of 0x%x is %i", ov
, (0x6996 >> v
) & 1);
758 return (0x6996 >> v
) & 1;
761 int xscale_load_ic(target_t
*target
, int mini
, uint32_t va
, uint32_t buffer
[8])
763 armv4_5_common_t
*armv4_5
= target
->arch_info
;
764 xscale_common_t
*xscale
= armv4_5
->arch_info
;
769 scan_field_t fields
[2];
771 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32
"", va
);
773 jtag_set_end_state(TAP_IDLE
);
774 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.ldic
); /* LDIC */
776 /* CMD is b010 for Main IC and b011 for Mini IC */
778 buf_set_u32(&cmd
, 0, 3, 0x3);
780 buf_set_u32(&cmd
, 0, 3, 0x2);
782 buf_set_u32(&cmd
, 3, 3, 0x0);
784 /* virtual address of desired cache line */
785 buf_set_u32(packet
, 0, 27, va
>> 5);
787 fields
[0].tap
= xscale
->jtag_info
.tap
;
788 fields
[0].num_bits
= 6;
789 fields
[0].out_value
= &cmd
;
791 fields
[0].in_value
= NULL
;
797 fields
[1].tap
= xscale
->jtag_info
.tap
;
798 fields
[1].num_bits
= 27;
799 fields
[1].out_value
= packet
;
801 fields
[1].in_value
= NULL
;
807 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
809 fields
[0].num_bits
= 32;
810 fields
[0].out_value
= packet
;
812 fields
[1].num_bits
= 1;
813 fields
[1].out_value
= &cmd
;
815 for (word
= 0; word
< 8; word
++)
817 buf_set_u32(packet
, 0, 32, buffer
[word
]);
820 memcpy(&value
, packet
, sizeof(uint32_t));
823 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
826 jtag_execute_queue();
831 int xscale_invalidate_ic_line(target_t
*target
, uint32_t va
)
833 armv4_5_common_t
*armv4_5
= target
->arch_info
;
834 xscale_common_t
*xscale
= armv4_5
->arch_info
;
838 scan_field_t fields
[2];
840 jtag_set_end_state(TAP_IDLE
);
841 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.ldic
); /* LDIC */
843 /* CMD for invalidate IC line b000, bits [6:4] b000 */
844 buf_set_u32(&cmd
, 0, 6, 0x0);
846 /* virtual address of desired cache line */
847 buf_set_u32(packet
, 0, 27, va
>> 5);
849 fields
[0].tap
= xscale
->jtag_info
.tap
;
850 fields
[0].num_bits
= 6;
851 fields
[0].out_value
= &cmd
;
853 fields
[0].in_value
= NULL
;
859 fields
[1].tap
= xscale
->jtag_info
.tap
;
860 fields
[1].num_bits
= 27;
861 fields
[1].out_value
= packet
;
863 fields
[1].in_value
= NULL
;
869 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
874 int xscale_update_vectors(target_t
*target
)
876 armv4_5_common_t
*armv4_5
= target
->arch_info
;
877 xscale_common_t
*xscale
= armv4_5
->arch_info
;
881 uint32_t low_reset_branch
, high_reset_branch
;
883 for (i
= 1; i
< 8; i
++)
885 /* if there's a static vector specified for this exception, override */
886 if (xscale
->static_high_vectors_set
& (1 << i
))
888 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
892 retval
= target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
893 if (retval
== ERROR_TARGET_TIMEOUT
)
895 if (retval
!= ERROR_OK
)
897 /* Some of these reads will fail as part of normal execution */
898 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
903 for (i
= 1; i
< 8; i
++)
905 if (xscale
->static_low_vectors_set
& (1 << i
))
907 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
911 retval
= target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
912 if (retval
== ERROR_TARGET_TIMEOUT
)
914 if (retval
!= ERROR_OK
)
916 /* Some of these reads will fail as part of normal execution */
917 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
922 /* calculate branches to debug handler */
923 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
924 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
926 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
927 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
929 /* invalidate and load exception vectors in mini i-cache */
930 xscale_invalidate_ic_line(target
, 0x0);
931 xscale_invalidate_ic_line(target
, 0xffff0000);
933 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
934 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
939 int xscale_arch_state(struct target_s
*target
)
941 armv4_5_common_t
*armv4_5
= target
->arch_info
;
942 xscale_common_t
*xscale
= armv4_5
->arch_info
;
946 "disabled", "enabled"
949 char *arch_dbg_reason
[] =
951 "", "\n(processor reset)", "\n(trace buffer full)"
954 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
956 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
960 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
961 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
962 "MMU: %s, D-Cache: %s, I-Cache: %s"
964 armv4_5_state_strings
[armv4_5
->core_state
],
965 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
966 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
967 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
968 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
969 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
970 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
971 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
972 arch_dbg_reason
[xscale
->arch_debug_reason
]);
977 int xscale_poll(target_t
*target
)
979 int retval
= ERROR_OK
;
980 armv4_5_common_t
*armv4_5
= target
->arch_info
;
981 xscale_common_t
*xscale
= armv4_5
->arch_info
;
983 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
985 enum target_state previous_state
= target
->state
;
986 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
989 /* there's data to read from the tx register, we entered debug state */
990 xscale
->handler_running
= 1;
992 target
->state
= TARGET_HALTED
;
994 /* process debug entry, fetching current mode regs */
995 retval
= xscale_debug_entry(target
);
997 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
999 LOG_USER("error while polling TX register, reset CPU");
1000 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1001 target
->state
= TARGET_HALTED
;
1004 /* debug_entry could have overwritten target state (i.e. immediate resume)
1005 * don't signal event handlers in that case
1007 if (target
->state
!= TARGET_HALTED
)
1010 /* if target was running, signal that we halted
1011 * otherwise we reentered from debug execution */
1012 if (previous_state
== TARGET_RUNNING
)
1013 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1015 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1021 int xscale_debug_entry(target_t
*target
)
1023 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1024 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1026 uint32_t buffer
[10];
1032 /* clear external dbg break (will be written on next DCSR read) */
1033 xscale
->external_debug_break
= 0;
1034 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1037 /* get r0, pc, r1 to r7 and cpsr */
1038 if ((retval
= xscale_receive(target
, buffer
, 10)) != ERROR_OK
)
1041 /* move r0 from buffer to register cache */
1042 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
1043 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1044 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1045 LOG_DEBUG("r0: 0x%8.8" PRIx32
"", buffer
[0]);
1047 /* move pc from buffer to register cache */
1048 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
1049 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1050 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1051 LOG_DEBUG("pc: 0x%8.8" PRIx32
"", buffer
[1]);
1053 /* move data from buffer to register cache */
1054 for (i
= 1; i
<= 7; i
++)
1056 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
1057 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
1058 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
1059 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, buffer
[i
+ 1]);
1062 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
1063 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1064 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1065 LOG_DEBUG("cpsr: 0x%8.8" PRIx32
"", buffer
[9]);
1067 armv4_5
->core_mode
= buffer
[9] & 0x1f;
1068 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1070 target
->state
= TARGET_UNKNOWN
;
1071 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1072 return ERROR_TARGET_FAILURE
;
1074 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1076 if (buffer
[9] & 0x20)
1077 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1079 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1082 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1085 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1086 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1088 xscale_receive(target
, buffer
, 8);
1089 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1090 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1091 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1095 /* r8 to r14, but no spsr */
1096 xscale_receive(target
, buffer
, 7);
1099 /* move data from buffer to register cache */
1100 for (i
= 8; i
<= 14; i
++)
1102 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1103 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1104 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1107 /* examine debug reason */
1108 xscale_read_dcsr(target
);
1109 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1111 /* stored PC (for calculating fixup) */
1112 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1116 case 0x0: /* Processor reset */
1117 target
->debug_reason
= DBG_REASON_DBGRQ
;
1118 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1121 case 0x1: /* Instruction breakpoint hit */
1122 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1123 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1126 case 0x2: /* Data breakpoint hit */
1127 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1128 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1131 case 0x3: /* BKPT instruction executed */
1132 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1133 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1136 case 0x4: /* Ext. debug event */
1137 target
->debug_reason
= DBG_REASON_DBGRQ
;
1138 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1141 case 0x5: /* Vector trap occured */
1142 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1143 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1146 case 0x6: /* Trace buffer full break */
1147 target
->debug_reason
= DBG_REASON_DBGRQ
;
1148 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1151 case 0x7: /* Reserved */
1153 LOG_ERROR("Method of Entry is 'Reserved'");
1158 /* apply PC fixup */
1159 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1161 /* on the first debug entry, identify cache type */
1162 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1164 uint32_t cache_type_reg
;
1166 /* read cp15 cache type register */
1167 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1168 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1170 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1173 /* examine MMU and Cache settings */
1174 /* read cp15 control register */
1175 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1176 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1177 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1178 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1179 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1181 /* tracing enabled, read collected trace data */
1182 if (xscale
->trace
.buffer_enabled
)
1184 xscale_read_trace(target
);
1185 xscale
->trace
.buffer_fill
--;
1187 /* resume if we're still collecting trace data */
1188 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1189 && (xscale
->trace
.buffer_fill
> 0))
1191 xscale_resume(target
, 1, 0x0, 1, 0);
1195 xscale
->trace
.buffer_enabled
= 0;
1202 int xscale_halt(target_t
*target
)
1204 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1205 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1207 LOG_DEBUG("target->state: %s",
1208 target_state_name(target
));
1210 if (target
->state
== TARGET_HALTED
)
1212 LOG_DEBUG("target was already halted");
1215 else if (target
->state
== TARGET_UNKNOWN
)
1217 /* this must not happen for a xscale target */
1218 LOG_ERROR("target was in unknown state when halt was requested");
1219 return ERROR_TARGET_INVALID
;
1221 else if (target
->state
== TARGET_RESET
)
1223 LOG_DEBUG("target->state == TARGET_RESET");
1227 /* assert external dbg break */
1228 xscale
->external_debug_break
= 1;
1229 xscale_read_dcsr(target
);
1231 target
->debug_reason
= DBG_REASON_DBGRQ
;
1237 int xscale_enable_single_step(struct target_s
*target
, uint32_t next_pc
)
1239 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1240 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1241 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1244 if (xscale
->ibcr0_used
)
1246 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1250 xscale_unset_breakpoint(target
, ibcr0_bp
);
1254 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1259 if ((retval
= xscale_set_reg_u32(ibcr0
, next_pc
| 0x1)) != ERROR_OK
)
1265 int xscale_disable_single_step(struct target_s
*target
)
1267 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1268 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1269 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1272 if ((retval
= xscale_set_reg_u32(ibcr0
, 0x0)) != ERROR_OK
)
1278 int xscale_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
1280 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1281 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1282 breakpoint_t
*breakpoint
= target
->breakpoints
;
1284 uint32_t current_pc
;
1291 if (target
->state
!= TARGET_HALTED
)
1293 LOG_WARNING("target not halted");
1294 return ERROR_TARGET_NOT_HALTED
;
1297 if (!debug_execution
)
1299 target_free_all_working_areas(target
);
1302 /* update vector tables */
1303 if ((retval
= xscale_update_vectors(target
)) != ERROR_OK
)
1306 /* current = 1: continue on current pc, otherwise continue at <address> */
1308 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1310 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1312 /* if we're at the reset vector, we have to simulate the branch */
1313 if (current_pc
== 0x0)
1315 arm_simulate_step(target
, NULL
);
1316 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1319 /* the front-end may request us not to handle breakpoints */
1320 if (handle_breakpoints
)
1322 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1326 /* there's a breakpoint at the current PC, we have to step over it */
1327 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1328 xscale_unset_breakpoint(target
, breakpoint
);
1330 /* calculate PC of next instruction */
1331 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1333 uint32_t current_opcode
;
1334 target_read_u32(target
, current_pc
, ¤t_opcode
);
1335 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1338 LOG_DEBUG("enable single-step");
1339 xscale_enable_single_step(target
, next_pc
);
1341 /* restore banked registers */
1342 xscale_restore_context(target
);
1344 /* send resume request (command 0x30 or 0x31)
1345 * clean the trace buffer if it is to be enabled (0x62) */
1346 if (xscale
->trace
.buffer_enabled
)
1348 xscale_send_u32(target
, 0x62);
1349 xscale_send_u32(target
, 0x31);
1352 xscale_send_u32(target
, 0x30);
1355 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1356 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1358 for (i
= 7; i
>= 0; i
--)
1361 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1362 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1366 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1367 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1369 /* wait for and process debug entry */
1370 xscale_debug_entry(target
);
1372 LOG_DEBUG("disable single-step");
1373 xscale_disable_single_step(target
);
1375 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1376 xscale_set_breakpoint(target
, breakpoint
);
1380 /* enable any pending breakpoints and watchpoints */
1381 xscale_enable_breakpoints(target
);
1382 xscale_enable_watchpoints(target
);
1384 /* restore banked registers */
1385 xscale_restore_context(target
);
1387 /* send resume request (command 0x30 or 0x31)
1388 * clean the trace buffer if it is to be enabled (0x62) */
1389 if (xscale
->trace
.buffer_enabled
)
1391 xscale_send_u32(target
, 0x62);
1392 xscale_send_u32(target
, 0x31);
1395 xscale_send_u32(target
, 0x30);
1398 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1399 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1401 for (i
= 7; i
>= 0; i
--)
1404 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1405 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1409 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1410 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1412 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1414 if (!debug_execution
)
1416 /* registers are now invalid */
1417 armv4_5_invalidate_core_regs(target
);
1418 target
->state
= TARGET_RUNNING
;
1419 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1423 target
->state
= TARGET_DEBUG_RUNNING
;
1424 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1427 LOG_DEBUG("target resumed");
1429 xscale
->handler_running
= 1;
1434 static int xscale_step_inner(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
)
1436 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1437 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1443 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1445 /* calculate PC of next instruction */
1446 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1448 uint32_t current_opcode
, current_pc
;
1449 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1451 target_read_u32(target
, current_pc
, ¤t_opcode
);
1452 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1456 LOG_DEBUG("enable single-step");
1457 if ((retval
= xscale_enable_single_step(target
, next_pc
)) != ERROR_OK
)
1460 /* restore banked registers */
1461 if ((retval
= xscale_restore_context(target
)) != ERROR_OK
)
1464 /* send resume request (command 0x30 or 0x31)
1465 * clean the trace buffer if it is to be enabled (0x62) */
1466 if (xscale
->trace
.buffer_enabled
)
1468 if ((retval
= xscale_send_u32(target
, 0x62)) != ERROR_OK
)
1470 if ((retval
= xscale_send_u32(target
, 0x31)) != ERROR_OK
)
1474 if ((retval
= xscale_send_u32(target
, 0x30)) != ERROR_OK
)
1478 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32))) != ERROR_OK
)
1480 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1482 for (i
= 7; i
>= 0; i
--)
1485 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32))) != ERROR_OK
)
1487 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1491 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))) != ERROR_OK
)
1493 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1495 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1497 /* registers are now invalid */
1498 if ((retval
= armv4_5_invalidate_core_regs(target
)) != ERROR_OK
)
1501 /* wait for and process debug entry */
1502 if ((retval
= xscale_debug_entry(target
)) != ERROR_OK
)
1505 LOG_DEBUG("disable single-step");
1506 if ((retval
= xscale_disable_single_step(target
)) != ERROR_OK
)
1509 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1514 int xscale_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
)
1516 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1517 breakpoint_t
*breakpoint
= target
->breakpoints
;
1519 uint32_t current_pc
;
1522 if (target
->state
!= TARGET_HALTED
)
1524 LOG_WARNING("target not halted");
1525 return ERROR_TARGET_NOT_HALTED
;
1528 /* current = 1: continue on current pc, otherwise continue at <address> */
1530 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1532 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1534 /* if we're at the reset vector, we have to simulate the step */
1535 if (current_pc
== 0x0)
1537 if ((retval
= arm_simulate_step(target
, NULL
)) != ERROR_OK
)
1539 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1541 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1542 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1547 /* the front-end may request us not to handle breakpoints */
1548 if (handle_breakpoints
)
1549 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1551 if ((retval
= xscale_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1555 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1559 xscale_set_breakpoint(target
, breakpoint
);
1562 LOG_DEBUG("target stepped");
1568 int xscale_assert_reset(target_t
*target
)
1570 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1571 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1573 LOG_DEBUG("target->state: %s",
1574 target_state_name(target
));
1576 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1577 * end up in T-L-R, which would reset JTAG
1579 jtag_set_end_state(TAP_IDLE
);
1580 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, xscale
->jtag_info
.dcsr
);
1582 /* set Hold reset, Halt mode and Trap Reset */
1583 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1584 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1585 xscale_write_dcsr(target
, 1, 0);
1587 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1588 xscale_jtag_set_instr(xscale
->jtag_info
.tap
, 0x7f);
1589 jtag_execute_queue();
1592 jtag_add_reset(0, 1);
1594 /* sleep 1ms, to be sure we fulfill any requirements */
1595 jtag_add_sleep(1000);
1596 jtag_execute_queue();
1598 target
->state
= TARGET_RESET
;
1600 if (target
->reset_halt
)
1603 if ((retval
= target_halt(target
)) != ERROR_OK
)
1610 int xscale_deassert_reset(target_t
*target
)
1612 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1613 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1615 fileio_t debug_handler
;
1617 uint32_t binary_size
;
1623 breakpoint_t
*breakpoint
= target
->breakpoints
;
1627 xscale
->ibcr_available
= 2;
1628 xscale
->ibcr0_used
= 0;
1629 xscale
->ibcr1_used
= 0;
1631 xscale
->dbr_available
= 2;
1632 xscale
->dbr0_used
= 0;
1633 xscale
->dbr1_used
= 0;
1635 /* mark all hardware breakpoints as unset */
1638 if (breakpoint
->type
== BKPT_HARD
)
1640 breakpoint
->set
= 0;
1642 breakpoint
= breakpoint
->next
;
1645 if (!xscale
->handler_installed
)
1648 jtag_add_reset(0, 0);
1650 /* wait 300ms; 150 and 100ms were not enough */
1651 jtag_add_sleep(300*1000);
1653 jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE
));
1654 jtag_execute_queue();
1656 /* set Hold reset, Halt mode and Trap Reset */
1657 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1658 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1659 xscale_write_dcsr(target
, 1, 0);
1661 /* Load debug handler */
1662 if (fileio_open(&debug_handler
, "xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1667 if ((binary_size
= debug_handler
.size
) % 4)
1669 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1673 if (binary_size
> 0x800)
1675 LOG_ERROR("debug_handler.bin: larger than 2kb");
1679 binary_size
= CEIL(binary_size
, 32) * 32;
1681 address
= xscale
->handler_address
;
1682 while (binary_size
> 0)
1684 uint32_t cache_line
[8];
1687 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1692 for (i
= 0; i
< buf_cnt
; i
+= 4)
1694 /* convert LE buffer to host-endian uint32_t */
1695 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1698 for (; buf_cnt
< 32; buf_cnt
+= 4)
1700 cache_line
[buf_cnt
/ 4] = 0xe1a08008;
1703 /* only load addresses other than the reset vectors */
1704 if ((address
% 0x400) != 0x0)
1706 xscale_load_ic(target
, 1, address
, cache_line
);
1710 binary_size
-= buf_cnt
;
1713 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
1714 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
1716 jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE
));
1718 jtag_add_sleep(100000);
1720 /* set Hold reset, Halt mode and Trap Reset */
1721 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1722 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1723 xscale_write_dcsr(target
, 1, 0);
1725 /* clear Hold reset to let the target run (should enter debug handler) */
1726 xscale_write_dcsr(target
, 0, 1);
1727 target
->state
= TARGET_RUNNING
;
1729 if (!target
->reset_halt
)
1731 jtag_add_sleep(10000);
1733 /* we should have entered debug now */
1734 xscale_debug_entry(target
);
1735 target
->state
= TARGET_HALTED
;
1737 /* resume the target */
1738 xscale_resume(target
, 1, 0x0, 1, 0);
1741 fileio_close(&debug_handler
);
1745 jtag_add_reset(0, 0);
1751 int xscale_soft_reset_halt(struct target_s
*target
)
1756 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1761 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, uint32_t value
)
1767 int xscale_full_context(target_t
*target
)
1769 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1777 if (target
->state
!= TARGET_HALTED
)
1779 LOG_WARNING("target not halted");
1780 return ERROR_TARGET_NOT_HALTED
;
1783 buffer
= malloc(4 * 8);
1785 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1786 * we can't enter User mode on an XScale (unpredictable),
1787 * but User shares registers with SYS
1789 for (i
= 1; i
< 7; i
++)
1793 /* check if there are invalid registers in the current mode
1795 for (j
= 0; j
<= 16; j
++)
1797 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1805 /* request banked registers */
1806 xscale_send_u32(target
, 0x0);
1809 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1810 tmp_cpsr
|= 0xc0; /* I/F bits */
1812 /* send CPSR for desired mode */
1813 xscale_send_u32(target
, tmp_cpsr
);
1815 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1816 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1818 xscale_receive(target
, buffer
, 8);
1819 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1820 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1821 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1825 xscale_receive(target
, buffer
, 7);
1828 /* move data from buffer to register cache */
1829 for (j
= 8; j
<= 14; j
++)
1831 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1832 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1833 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1843 int xscale_restore_context(target_t
*target
)
1845 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1851 if (target
->state
!= TARGET_HALTED
)
1853 LOG_WARNING("target not halted");
1854 return ERROR_TARGET_NOT_HALTED
;
1857 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1858 * we can't enter User mode on an XScale (unpredictable),
1859 * but User shares registers with SYS
1861 for (i
= 1; i
< 7; i
++)
1865 /* check if there are invalid registers in the current mode
1867 for (j
= 8; j
<= 14; j
++)
1869 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1873 /* if not USR/SYS, check if the SPSR needs to be written */
1874 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1876 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1884 /* send banked registers */
1885 xscale_send_u32(target
, 0x1);
1888 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1889 tmp_cpsr
|= 0xc0; /* I/F bits */
1891 /* send CPSR for desired mode */
1892 xscale_send_u32(target
, tmp_cpsr
);
1894 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1895 for (j
= 8; j
<= 14; j
++)
1897 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1898 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1901 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1903 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1904 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1912 int xscale_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1914 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1915 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1920 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1922 if (target
->state
!= TARGET_HALTED
)
1924 LOG_WARNING("target not halted");
1925 return ERROR_TARGET_NOT_HALTED
;
1928 /* sanitize arguments */
1929 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1930 return ERROR_INVALID_ARGUMENTS
;
1932 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1933 return ERROR_TARGET_UNALIGNED_ACCESS
;
1935 /* send memory read request (command 0x1n, n: access size) */
1936 if ((retval
= xscale_send_u32(target
, 0x10 | size
)) != ERROR_OK
)
1939 /* send base address for read request */
1940 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1943 /* send number of requested data words */
1944 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1947 /* receive data from target (count times 32-bit words in host endianness) */
1948 buf32
= malloc(4 * count
);
1949 if ((retval
= xscale_receive(target
, buf32
, count
)) != ERROR_OK
)
1952 /* extract data from host-endian buffer into byte stream */
1953 for (i
= 0; i
< count
; i
++)
1958 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1962 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1966 *buffer
++ = buf32
[i
] & 0xff;
1969 LOG_ERROR("should never get here");
1976 /* examine DCSR, to see if Sticky Abort (SA) got set */
1977 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1979 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1982 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1985 return ERROR_TARGET_DATA_ABORT
;
1991 int xscale_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1993 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1994 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1997 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1999 if (target
->state
!= TARGET_HALTED
)
2001 LOG_WARNING("target not halted");
2002 return ERROR_TARGET_NOT_HALTED
;
2005 /* sanitize arguments */
2006 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2007 return ERROR_INVALID_ARGUMENTS
;
2009 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2010 return ERROR_TARGET_UNALIGNED_ACCESS
;
2012 /* send memory write request (command 0x2n, n: access size) */
2013 if ((retval
= xscale_send_u32(target
, 0x20 | size
)) != ERROR_OK
)
2016 /* send base address for read request */
2017 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
2020 /* send number of requested data words to be written*/
2021 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
2024 /* extract data from host-endian buffer into byte stream */
2026 for (i
= 0; i
< count
; i
++)
2031 value
= target_buffer_get_u32(target
, buffer
);
2032 xscale_send_u32(target
, value
);
2036 value
= target_buffer_get_u16(target
, buffer
);
2037 xscale_send_u32(target
, value
);
2042 xscale_send_u32(target
, value
);
2046 LOG_ERROR("should never get here");
2051 if ((retval
= xscale_send(target
, buffer
, count
, size
)) != ERROR_OK
)
2054 /* examine DCSR, to see if Sticky Abort (SA) got set */
2055 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
2057 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2060 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
2063 return ERROR_TARGET_DATA_ABORT
;
2069 int xscale_bulk_write_memory(target_t
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
2071 return xscale_write_memory(target
, address
, 4, count
, buffer
);
2074 uint32_t xscale_get_ttb(target_t
*target
)
2076 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2077 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2080 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2081 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2086 void xscale_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2088 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2089 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2090 uint32_t cp15_control
;
2092 /* read cp15 control register */
2093 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2094 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2097 cp15_control
&= ~0x1U
;
2102 xscale_send_u32(target
, 0x50);
2103 xscale_send_u32(target
, xscale
->cache_clean_address
);
2105 /* invalidate DCache */
2106 xscale_send_u32(target
, 0x51);
2108 cp15_control
&= ~0x4U
;
2113 /* invalidate ICache */
2114 xscale_send_u32(target
, 0x52);
2115 cp15_control
&= ~0x1000U
;
2118 /* write new cp15 control register */
2119 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2121 /* execute cpwait to ensure outstanding operations complete */
2122 xscale_send_u32(target
, 0x53);
2125 void xscale_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2127 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2128 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2129 uint32_t cp15_control
;
2131 /* read cp15 control register */
2132 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2133 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2136 cp15_control
|= 0x1U
;
2139 cp15_control
|= 0x4U
;
2142 cp15_control
|= 0x1000U
;
2144 /* write new cp15 control register */
2145 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2147 /* execute cpwait to ensure outstanding operations complete */
2148 xscale_send_u32(target
, 0x53);
2151 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2154 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2155 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2157 if (target
->state
!= TARGET_HALTED
)
2159 LOG_WARNING("target not halted");
2160 return ERROR_TARGET_NOT_HALTED
;
2163 if (breakpoint
->set
)
2165 LOG_WARNING("breakpoint already set");
2169 if (breakpoint
->type
== BKPT_HARD
)
2171 uint32_t value
= breakpoint
->address
| 1;
2172 if (!xscale
->ibcr0_used
)
2174 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2175 xscale
->ibcr0_used
= 1;
2176 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2178 else if (!xscale
->ibcr1_used
)
2180 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2181 xscale
->ibcr1_used
= 1;
2182 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2186 LOG_ERROR("BUG: no hardware comparator available");
2190 else if (breakpoint
->type
== BKPT_SOFT
)
2192 if (breakpoint
->length
== 4)
2194 /* keep the original instruction in target endianness */
2195 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2199 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2200 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
)) != ERROR_OK
)
2207 /* keep the original instruction in target endianness */
2208 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2212 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2213 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
)) != ERROR_OK
)
2218 breakpoint
->set
= 1;
2224 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2226 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2227 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2229 if (target
->state
!= TARGET_HALTED
)
2231 LOG_WARNING("target not halted");
2232 return ERROR_TARGET_NOT_HALTED
;
2235 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2237 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2238 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2241 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2243 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2244 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2247 if (breakpoint
->type
== BKPT_HARD
)
2249 xscale
->ibcr_available
--;
2255 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2258 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2259 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2261 if (target
->state
!= TARGET_HALTED
)
2263 LOG_WARNING("target not halted");
2264 return ERROR_TARGET_NOT_HALTED
;
2267 if (!breakpoint
->set
)
2269 LOG_WARNING("breakpoint not set");
2273 if (breakpoint
->type
== BKPT_HARD
)
2275 if (breakpoint
->set
== 1)
2277 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2278 xscale
->ibcr0_used
= 0;
2280 else if (breakpoint
->set
== 2)
2282 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2283 xscale
->ibcr1_used
= 0;
2285 breakpoint
->set
= 0;
2289 /* restore original instruction (kept in target endianness) */
2290 if (breakpoint
->length
== 4)
2292 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2299 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2304 breakpoint
->set
= 0;
2310 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2312 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2313 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2315 if (target
->state
!= TARGET_HALTED
)
2317 LOG_WARNING("target not halted");
2318 return ERROR_TARGET_NOT_HALTED
;
2321 if (breakpoint
->set
)
2323 xscale_unset_breakpoint(target
, breakpoint
);
2326 if (breakpoint
->type
== BKPT_HARD
)
2327 xscale
->ibcr_available
++;
2332 int xscale_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2334 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2335 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2337 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2338 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2340 if (target
->state
!= TARGET_HALTED
)
2342 LOG_WARNING("target not halted");
2343 return ERROR_TARGET_NOT_HALTED
;
2346 xscale_get_reg(dbcon
);
2348 switch (watchpoint
->rw
)
2360 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2363 if (!xscale
->dbr0_used
)
2365 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2366 dbcon_value
|= enable
;
2367 xscale_set_reg_u32(dbcon
, dbcon_value
);
2368 watchpoint
->set
= 1;
2369 xscale
->dbr0_used
= 1;
2371 else if (!xscale
->dbr1_used
)
2373 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2374 dbcon_value
|= enable
<< 2;
2375 xscale_set_reg_u32(dbcon
, dbcon_value
);
2376 watchpoint
->set
= 2;
2377 xscale
->dbr1_used
= 1;
2381 LOG_ERROR("BUG: no hardware comparator available");
2388 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2390 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2391 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2393 if (target
->state
!= TARGET_HALTED
)
2395 LOG_WARNING("target not halted");
2396 return ERROR_TARGET_NOT_HALTED
;
2399 if (xscale
->dbr_available
< 1)
2401 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2404 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2406 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2409 xscale
->dbr_available
--;
2414 int xscale_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2416 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2417 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2418 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2419 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2421 if (target
->state
!= TARGET_HALTED
)
2423 LOG_WARNING("target not halted");
2424 return ERROR_TARGET_NOT_HALTED
;
2427 if (!watchpoint
->set
)
2429 LOG_WARNING("breakpoint not set");
2433 if (watchpoint
->set
== 1)
2435 dbcon_value
&= ~0x3;
2436 xscale_set_reg_u32(dbcon
, dbcon_value
);
2437 xscale
->dbr0_used
= 0;
2439 else if (watchpoint
->set
== 2)
2441 dbcon_value
&= ~0xc;
2442 xscale_set_reg_u32(dbcon
, dbcon_value
);
2443 xscale
->dbr1_used
= 0;
2445 watchpoint
->set
= 0;
2450 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2452 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2453 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2455 if (target
->state
!= TARGET_HALTED
)
2457 LOG_WARNING("target not halted");
2458 return ERROR_TARGET_NOT_HALTED
;
2461 if (watchpoint
->set
)
2463 xscale_unset_watchpoint(target
, watchpoint
);
2466 xscale
->dbr_available
++;
2471 void xscale_enable_watchpoints(struct target_s
*target
)
2473 watchpoint_t
*watchpoint
= target
->watchpoints
;
2477 if (watchpoint
->set
== 0)
2478 xscale_set_watchpoint(target
, watchpoint
);
2479 watchpoint
= watchpoint
->next
;
2483 void xscale_enable_breakpoints(struct target_s
*target
)
2485 breakpoint_t
*breakpoint
= target
->breakpoints
;
2487 /* set any pending breakpoints */
2490 if (breakpoint
->set
== 0)
2491 xscale_set_breakpoint(target
, breakpoint
);
2492 breakpoint
= breakpoint
->next
;
2496 int xscale_get_reg(reg_t
*reg
)
2498 xscale_reg_t
*arch_info
= reg
->arch_info
;
2499 target_t
*target
= arch_info
->target
;
2500 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2501 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2503 /* DCSR, TX and RX are accessible via JTAG */
2504 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2506 return xscale_read_dcsr(arch_info
->target
);
2508 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2510 /* 1 = consume register content */
2511 return xscale_read_tx(arch_info
->target
, 1);
2513 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2515 /* can't read from RX register (host -> debug handler) */
2518 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2520 /* can't (explicitly) read from TXRXCTRL register */
2523 else /* Other DBG registers have to be transfered by the debug handler */
2525 /* send CP read request (command 0x40) */
2526 xscale_send_u32(target
, 0x40);
2528 /* send CP register number */
2529 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2531 /* read register value */
2532 xscale_read_tx(target
, 1);
2533 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2542 int xscale_set_reg(reg_t
*reg
, uint8_t* buf
)
2544 xscale_reg_t
*arch_info
= reg
->arch_info
;
2545 target_t
*target
= arch_info
->target
;
2546 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2547 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2548 uint32_t value
= buf_get_u32(buf
, 0, 32);
2550 /* DCSR, TX and RX are accessible via JTAG */
2551 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2553 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2554 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2556 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2558 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2559 return xscale_write_rx(arch_info
->target
);
2561 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2563 /* can't write to TX register (debug-handler -> host) */
2566 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2568 /* can't (explicitly) write to TXRXCTRL register */
2571 else /* Other DBG registers have to be transfered by the debug handler */
2573 /* send CP write request (command 0x41) */
2574 xscale_send_u32(target
, 0x41);
2576 /* send CP register number */
2577 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2579 /* send CP register value */
2580 xscale_send_u32(target
, value
);
2581 buf_set_u32(reg
->value
, 0, 32, value
);
2587 /* convenience wrapper to access XScale specific registers */
2588 int xscale_set_reg_u32(reg_t
*reg
, uint32_t value
)
2592 buf_set_u32(buf
, 0, 32, value
);
2594 return xscale_set_reg(reg
, buf
);
2597 int xscale_write_dcsr_sw(target_t
*target
, uint32_t value
)
2599 /* get pointers to arch-specific information */
2600 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2601 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2602 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2603 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2605 /* send CP write request (command 0x41) */
2606 xscale_send_u32(target
, 0x41);
2608 /* send CP register number */
2609 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2611 /* send CP register value */
2612 xscale_send_u32(target
, value
);
2613 buf_set_u32(dcsr
->value
, 0, 32, value
);
2618 int xscale_read_trace(target_t
*target
)
2620 /* get pointers to arch-specific information */
2621 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2622 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2623 xscale_trace_data_t
**trace_data_p
;
2625 /* 258 words from debug handler
2626 * 256 trace buffer entries
2627 * 2 checkpoint addresses
2629 uint32_t trace_buffer
[258];
2630 int is_address
[256];
2633 if (target
->state
!= TARGET_HALTED
)
2635 LOG_WARNING("target must be stopped to read trace data");
2636 return ERROR_TARGET_NOT_HALTED
;
2639 /* send read trace buffer command (command 0x61) */
2640 xscale_send_u32(target
, 0x61);
2642 /* receive trace buffer content */
2643 xscale_receive(target
, trace_buffer
, 258);
2645 /* parse buffer backwards to identify address entries */
2646 for (i
= 255; i
>= 0; i
--)
2649 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2650 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2653 is_address
[--i
] = 1;
2655 is_address
[--i
] = 1;
2657 is_address
[--i
] = 1;
2659 is_address
[--i
] = 1;
2664 /* search first non-zero entry */
2665 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2670 LOG_DEBUG("no trace data collected");
2671 return ERROR_XSCALE_NO_TRACE_DATA
;
2674 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2677 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2678 (*trace_data_p
)->next
= NULL
;
2679 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2680 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2681 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2682 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2683 (*trace_data_p
)->depth
= 256 - j
;
2685 for (i
= j
; i
< 256; i
++)
2687 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2689 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2691 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2697 int xscale_read_instruction(target_t
*target
, arm_instruction_t
*instruction
)
2699 /* get pointers to arch-specific information */
2700 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2701 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2708 if (!xscale
->trace
.image
)
2709 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2711 /* search for the section the current instruction belongs to */
2712 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2714 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2715 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2724 /* current instruction couldn't be found in the image */
2725 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2728 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2731 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2732 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2733 4, buf
, &size_read
)) != ERROR_OK
)
2735 LOG_ERROR("error while reading instruction: %i", retval
);
2736 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2738 opcode
= target_buffer_get_u32(target
, buf
);
2739 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2741 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2744 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2745 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2746 2, buf
, &size_read
)) != ERROR_OK
)
2748 LOG_ERROR("error while reading instruction: %i", retval
);
2749 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2751 opcode
= target_buffer_get_u16(target
, buf
);
2752 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2756 LOG_ERROR("BUG: unknown core state encountered");
2763 int xscale_branch_address(xscale_trace_data_t
*trace_data
, int i
, uint32_t *target
)
2765 /* if there are less than four entries prior to the indirect branch message
2766 * we can't extract the address */
2772 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2773 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2778 int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2780 /* get pointers to arch-specific information */
2781 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2782 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2784 uint32_t next_pc
= 0x0;
2785 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2794 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2799 for (i
= 0; i
< trace_data
->depth
; i
++)
2805 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2808 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2810 case 0: /* Exceptions */
2818 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2820 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2821 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2823 case 8: /* Direct Branch */
2826 case 9: /* Indirect Branch */
2828 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2833 case 13: /* Checkpointed Indirect Branch */
2834 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2837 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2838 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2839 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2841 /* explicit fall-through */
2842 case 12: /* Checkpointed Direct Branch */
2847 next_pc
= trace_data
->chkpt0
;
2850 else if (chkpt
== 1)
2853 next_pc
= trace_data
->chkpt0
;
2858 LOG_WARNING("more than two checkpointed branches encountered");
2861 case 15: /* Roll-over */
2864 default: /* Reserved */
2865 command_print(cmd_ctx
, "--- reserved trace message ---");
2866 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2870 if (xscale
->trace
.pc_ok
)
2872 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2873 arm_instruction_t instruction
;
2875 if ((exception
== 6) || (exception
== 7))
2877 /* IRQ or FIQ exception, no instruction executed */
2881 while (executed
-- >= 0)
2883 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2885 /* can't continue tracing with no image available */
2886 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2890 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2892 /* TODO: handle incomplete images */
2896 /* a precise abort on a load to the PC is included in the incremental
2897 * word count, other instructions causing data aborts are not included
2899 if ((executed
== 0) && (exception
== 4)
2900 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2902 if ((instruction
.type
== ARM_LDM
)
2903 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2907 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2908 && (instruction
.info
.load_store
.Rd
!= 15))
2914 /* only the last instruction executed
2915 * (the one that caused the control flow change)
2916 * could be a taken branch
2918 if (((executed
== -1) && (branch
== 1)) &&
2919 (((instruction
.type
== ARM_B
) ||
2920 (instruction
.type
== ARM_BL
) ||
2921 (instruction
.type
== ARM_BLX
)) &&
2922 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff)))
2924 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2928 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2930 command_print(cmd_ctx
, "%s", instruction
.text
);
2938 xscale
->trace
.current_pc
= next_pc
;
2939 xscale
->trace
.pc_ok
= 1;
2943 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2945 arm_instruction_t instruction
;
2946 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2948 /* can't continue tracing with no image available */
2949 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2953 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2955 /* TODO: handle incomplete images */
2958 command_print(cmd_ctx
, "%s", instruction
.text
);
2961 trace_data
= trace_data
->next
;
2967 void xscale_build_reg_cache(target_t
*target
)
2969 /* get pointers to arch-specific information */
2970 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2971 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2973 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2974 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2976 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2978 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2979 armv4_5
->core_cache
= (*cache_p
);
2981 /* register a register arch-type for XScale dbg registers only once */
2982 if (xscale_reg_arch_type
== -1)
2983 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
2985 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
2986 cache_p
= &(*cache_p
)->next
;
2988 /* fill in values for the xscale reg cache */
2989 (*cache_p
)->name
= "XScale registers";
2990 (*cache_p
)->next
= NULL
;
2991 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
2992 (*cache_p
)->num_regs
= num_regs
;
2994 for (i
= 0; i
< num_regs
; i
++)
2996 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2997 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2998 (*cache_p
)->reg_list
[i
].dirty
= 0;
2999 (*cache_p
)->reg_list
[i
].valid
= 0;
3000 (*cache_p
)->reg_list
[i
].size
= 32;
3001 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
3002 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
3003 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
3004 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
3005 arch_info
[i
] = xscale_reg_arch_info
[i
];
3006 arch_info
[i
].target
= target
;
3009 xscale
->reg_cache
= (*cache_p
);
3012 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
3017 int xscale_quit(void)
3022 int xscale_init_arch_info(target_t
*target
, xscale_common_t
*xscale
, jtag_tap_t
*tap
, const char *variant
)
3024 armv4_5_common_t
*armv4_5
;
3025 uint32_t high_reset_branch
, low_reset_branch
;
3028 armv4_5
= &xscale
->armv4_5_common
;
3030 /* store architecture specfic data (none so far) */
3031 xscale
->arch_info
= NULL
;
3032 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
3034 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3035 xscale
->variant
= strdup(variant
);
3037 /* prepare JTAG information for the new target */
3038 xscale
->jtag_info
.tap
= tap
;
3040 xscale
->jtag_info
.dbgrx
= 0x02;
3041 xscale
->jtag_info
.dbgtx
= 0x10;
3042 xscale
->jtag_info
.dcsr
= 0x09;
3043 xscale
->jtag_info
.ldic
= 0x07;
3045 if ((strcmp(xscale
->variant
, "pxa250") == 0) ||
3046 (strcmp(xscale
->variant
, "pxa255") == 0) ||
3047 (strcmp(xscale
->variant
, "pxa26x") == 0))
3049 xscale
->jtag_info
.ir_length
= 5;
3051 else if ((strcmp(xscale
->variant
, "pxa27x") == 0) ||
3052 (strcmp(xscale
->variant
, "ixp42x") == 0) ||
3053 (strcmp(xscale
->variant
, "ixp45x") == 0) ||
3054 (strcmp(xscale
->variant
, "ixp46x") == 0))
3056 xscale
->jtag_info
.ir_length
= 7;
3059 /* the debug handler isn't installed (and thus not running) at this time */
3060 xscale
->handler_installed
= 0;
3061 xscale
->handler_running
= 0;
3062 xscale
->handler_address
= 0xfe000800;
3064 /* clear the vectors we keep locally for reference */
3065 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
3066 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
3068 /* no user-specified vectors have been configured yet */
3069 xscale
->static_low_vectors_set
= 0x0;
3070 xscale
->static_high_vectors_set
= 0x0;
3072 /* calculate branches to debug handler */
3073 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
3074 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3076 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3077 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3079 for (i
= 1; i
<= 7; i
++)
3081 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3082 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3085 /* 64kB aligned region used for DCache cleaning */
3086 xscale
->cache_clean_address
= 0xfffe0000;
3088 xscale
->hold_rst
= 0;
3089 xscale
->external_debug_break
= 0;
3091 xscale
->ibcr_available
= 2;
3092 xscale
->ibcr0_used
= 0;
3093 xscale
->ibcr1_used
= 0;
3095 xscale
->dbr_available
= 2;
3096 xscale
->dbr0_used
= 0;
3097 xscale
->dbr1_used
= 0;
3099 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3100 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3102 xscale
->vector_catch
= 0x1;
3104 xscale
->trace
.capture_status
= TRACE_IDLE
;
3105 xscale
->trace
.data
= NULL
;
3106 xscale
->trace
.image
= NULL
;
3107 xscale
->trace
.buffer_enabled
= 0;
3108 xscale
->trace
.buffer_fill
= 0;
3110 /* prepare ARMv4/5 specific information */
3111 armv4_5
->arch_info
= xscale
;
3112 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3113 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3114 armv4_5
->full_context
= xscale_full_context
;
3116 armv4_5_init_arch_info(target
, armv4_5
);
3118 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3119 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3120 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3121 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3122 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3123 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3124 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3125 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3130 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3131 int xscale_target_create(struct target_s
*target
, Jim_Interp
*interp
)
3133 xscale_common_t
*xscale
= calloc(1,sizeof(xscale_common_t
));
3135 xscale_init_arch_info(target
, xscale
, target
->tap
, target
->variant
);
3136 xscale_build_reg_cache(target
);
3141 int xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3143 target_t
*target
= NULL
;
3144 armv4_5_common_t
*armv4_5
;
3145 xscale_common_t
*xscale
;
3147 uint32_t handler_address
;
3151 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3155 if ((target
= get_target(args
[0])) == NULL
)
3157 LOG_ERROR("target '%s' not defined", args
[0]);
3161 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3166 handler_address
= strtoul(args
[1], NULL
, 0);
3168 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3169 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3171 xscale
->handler_address
= handler_address
;
3175 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3182 int xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3184 target_t
*target
= NULL
;
3185 armv4_5_common_t
*armv4_5
;
3186 xscale_common_t
*xscale
;
3188 uint32_t cache_clean_address
;
3192 return ERROR_COMMAND_SYNTAX_ERROR
;
3195 target
= get_target(args
[0]);
3198 LOG_ERROR("target '%s' not defined", args
[0]);
3202 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3207 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3209 if (cache_clean_address
& 0xffff)
3211 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3215 xscale
->cache_clean_address
= cache_clean_address
;
3221 int xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3223 target_t
*target
= get_current_target(cmd_ctx
);
3224 armv4_5_common_t
*armv4_5
;
3225 xscale_common_t
*xscale
;
3227 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3232 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3235 static int xscale_virt2phys(struct target_s
*target
, uint32_t virtual, uint32_t *physical
)
3237 armv4_5_common_t
*armv4_5
;
3238 xscale_common_t
*xscale
;
3245 if ((retval
= xscale_get_arch_pointers(target
, &armv4_5
, &xscale
)) != ERROR_OK
)
3249 uint32_t ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3258 static int xscale_mmu(struct target_s
*target
, int *enabled
)
3260 armv4_5_common_t
*armv4_5
= target
->arch_info
;
3261 xscale_common_t
*xscale
= armv4_5
->arch_info
;
3263 if (target
->state
!= TARGET_HALTED
)
3265 LOG_ERROR("Target not halted");
3266 return ERROR_TARGET_INVALID
;
3268 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3272 int xscale_handle_mmu_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3274 target_t
*target
= get_current_target(cmd_ctx
);
3275 armv4_5_common_t
*armv4_5
;
3276 xscale_common_t
*xscale
;
3278 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3283 if (target
->state
!= TARGET_HALTED
)
3285 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3291 if (strcmp("enable", args
[0]) == 0)
3293 xscale_enable_mmu_caches(target
, 1, 0, 0);
3294 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3296 else if (strcmp("disable", args
[0]) == 0)
3298 xscale_disable_mmu_caches(target
, 1, 0, 0);
3299 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3303 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3308 int xscale_handle_idcache_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3310 target_t
*target
= get_current_target(cmd_ctx
);
3311 armv4_5_common_t
*armv4_5
;
3312 xscale_common_t
*xscale
;
3313 int icache
= 0, dcache
= 0;
3315 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3320 if (target
->state
!= TARGET_HALTED
)
3322 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3326 if (strcmp(cmd
, "icache") == 0)
3328 else if (strcmp(cmd
, "dcache") == 0)
3333 if (strcmp("enable", args
[0]) == 0)
3335 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3338 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3340 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3342 else if (strcmp("disable", args
[0]) == 0)
3344 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3347 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3349 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3354 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3357 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3362 int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3364 target_t
*target
= get_current_target(cmd_ctx
);
3365 armv4_5_common_t
*armv4_5
;
3366 xscale_common_t
*xscale
;
3368 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3375 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3379 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3380 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3381 xscale_write_dcsr(target
, -1, -1);
3384 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3390 int xscale_handle_vector_table_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3392 target_t
*target
= get_current_target(cmd_ctx
);
3393 armv4_5_common_t
*armv4_5
;
3394 xscale_common_t
*xscale
;
3397 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3402 if (argc
== 0) /* print current settings */
3406 command_print(cmd_ctx
, "active user-set static vectors:");
3407 for (idx
= 1; idx
< 8; idx
++)
3408 if (xscale
->static_low_vectors_set
& (1 << idx
))
3409 command_print(cmd_ctx
, "low %d: 0x%x", idx
, xscale
->static_low_vectors
[idx
]);
3410 for (idx
= 1; idx
< 8; idx
++)
3411 if (xscale
->static_high_vectors_set
& (1 << idx
))
3412 command_print(cmd_ctx
, "high %d: 0x%x", idx
, xscale
->static_high_vectors
[idx
]);
3422 idx
= strtoul(args
[1], NULL
, 0);
3423 vec
= strtoul(args
[2], NULL
, 0);
3425 if (idx
< 1 || idx
>= 8)
3428 if (!err
&& strcmp(args
[0], "low") == 0)
3430 xscale
->static_low_vectors_set
|= (1<<idx
);
3431 xscale
->static_low_vectors
[idx
] = vec
;
3433 else if (!err
&& (strcmp(args
[0], "high") == 0))
3435 xscale
->static_high_vectors_set
|= (1<<idx
);
3436 xscale
->static_high_vectors
[idx
] = vec
;
3443 command_print(cmd_ctx
, "usage: xscale vector_table <high|low> <index> <code>");
3449 int xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3451 target_t
*target
= get_current_target(cmd_ctx
);
3452 armv4_5_common_t
*armv4_5
;
3453 xscale_common_t
*xscale
;
3454 uint32_t dcsr_value
;
3456 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3461 if (target
->state
!= TARGET_HALTED
)
3463 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3467 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3469 xscale_trace_data_t
*td
, *next_td
;
3470 xscale
->trace
.buffer_enabled
= 1;
3472 /* free old trace data */
3473 td
= xscale
->trace
.data
;
3483 xscale
->trace
.data
= NULL
;
3485 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3487 xscale
->trace
.buffer_enabled
= 0;
3490 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3493 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3495 xscale
->trace
.buffer_fill
= 1;
3497 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3499 xscale
->trace
.buffer_fill
= -1;
3502 if (xscale
->trace
.buffer_enabled
)
3504 /* if we enable the trace buffer in fill-once
3505 * mode we know the address of the first instruction */
3506 xscale
->trace
.pc_ok
= 1;
3507 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3511 /* otherwise the address is unknown, and we have no known good PC */
3512 xscale
->trace
.pc_ok
= 0;
3515 command_print(cmd_ctx
, "trace buffer %s (%s)",
3516 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3517 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3519 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3520 if (xscale
->trace
.buffer_fill
>= 0)
3521 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3523 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3528 int xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3531 armv4_5_common_t
*armv4_5
;
3532 xscale_common_t
*xscale
;
3536 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3540 target
= get_current_target(cmd_ctx
);
3542 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3547 if (xscale
->trace
.image
)
3549 image_close(xscale
->trace
.image
);
3550 free(xscale
->trace
.image
);
3551 command_print(cmd_ctx
, "previously loaded image found and closed");
3554 xscale
->trace
.image
= malloc(sizeof(image_t
));
3555 xscale
->trace
.image
->base_address_set
= 0;
3556 xscale
->trace
.image
->start_address_set
= 0;
3558 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3561 xscale
->trace
.image
->base_address_set
= 1;
3562 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3566 xscale
->trace
.image
->base_address_set
= 0;
3569 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3571 free(xscale
->trace
.image
);
3572 xscale
->trace
.image
= NULL
;
3579 int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3581 target_t
*target
= get_current_target(cmd_ctx
);
3582 armv4_5_common_t
*armv4_5
;
3583 xscale_common_t
*xscale
;
3584 xscale_trace_data_t
*trace_data
;
3587 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3592 if (target
->state
!= TARGET_HALTED
)
3594 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3600 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3604 trace_data
= xscale
->trace
.data
;
3608 command_print(cmd_ctx
, "no trace data collected");
3612 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3621 fileio_write_u32(&file
, trace_data
->chkpt0
);
3622 fileio_write_u32(&file
, trace_data
->chkpt1
);
3623 fileio_write_u32(&file
, trace_data
->last_instruction
);
3624 fileio_write_u32(&file
, trace_data
->depth
);
3626 for (i
= 0; i
< trace_data
->depth
; i
++)
3627 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3629 trace_data
= trace_data
->next
;
3632 fileio_close(&file
);
3637 int xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3639 target_t
*target
= get_current_target(cmd_ctx
);
3640 armv4_5_common_t
*armv4_5
;
3641 xscale_common_t
*xscale
;
3643 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3648 xscale_analyze_trace(target
, cmd_ctx
);
3653 int xscale_handle_cp15(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3655 target_t
*target
= get_current_target(cmd_ctx
);
3656 armv4_5_common_t
*armv4_5
;
3657 xscale_common_t
*xscale
;
3659 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3664 if (target
->state
!= TARGET_HALTED
)
3666 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3669 uint32_t reg_no
= 0;
3673 reg_no
= strtoul(args
[0], NULL
, 0);
3674 /*translate from xscale cp15 register no to openocd register*/
3678 reg_no
= XSCALE_MAINID
;
3681 reg_no
= XSCALE_CTRL
;
3684 reg_no
= XSCALE_TTB
;
3687 reg_no
= XSCALE_DAC
;
3690 reg_no
= XSCALE_FSR
;
3693 reg_no
= XSCALE_FAR
;
3696 reg_no
= XSCALE_PID
;
3699 reg_no
= XSCALE_CPACCESS
;
3702 command_print(cmd_ctx
, "invalid register number");
3703 return ERROR_INVALID_ARGUMENTS
;
3705 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3712 /* read cp15 control register */
3713 xscale_get_reg(reg
);
3714 value
= buf_get_u32(reg
->value
, 0, 32);
3715 command_print(cmd_ctx
, "%s (/%i): 0x%" PRIx32
"", reg
->name
, (int)(reg
->size
), value
);
3720 uint32_t value
= strtoul(args
[1], NULL
, 0);
3722 /* send CP write request (command 0x41) */
3723 xscale_send_u32(target
, 0x41);
3725 /* send CP register number */
3726 xscale_send_u32(target
, reg_no
);
3728 /* send CP register value */
3729 xscale_send_u32(target
, value
);
3731 /* execute cpwait to ensure outstanding operations complete */
3732 xscale_send_u32(target
, 0x53);
3736 command_print(cmd_ctx
, "usage: cp15 [register]<, [value]>");
3742 int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3744 command_t
*xscale_cmd
;
3746 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3748 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3749 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3751 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3752 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3753 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3754 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3756 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_vector_catch_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3757 register_command(cmd_ctx
, xscale_cmd
, "vector_table", xscale_handle_vector_table_command
, COMMAND_EXEC
, "<high|low> <index> <code> set static code for exception handler entry");
3759 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable | disable> ['fill' [n]|'wrap']");
3761 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3762 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3763 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3764 COMMAND_EXEC
, "load image from <file> [base address]");
3766 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3768 armv4_5_register_commands(cmd_ctx
);
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