src/target/xscale.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   8  *   oyvind.harboe@zylin.com                                               *
   9  ***************************************************************************/
  10
  11 #ifndef OPENOCD_TARGET_XSCALE_H
  12 #define OPENOCD_TARGET_XSCALE_H
  13
  14 #include "arm.h"
  15 #include "armv4_5_mmu.h"
  16 #include "trace.h"
  17
  18 #define XSCALE_COMMON_MAGIC 0x58534341U
  19
  20 /* These four JTAG instructions are architecturally defined.
  21  * Lengths are core-specific; originally 5 bits, later 7.
  22  */
  23 #define XSCALE_DBGRX    0x02
  24 #define XSCALE_DBGTX    0x10
  25 #define XSCALE_LDIC     0x07
  26 #define XSCALE_SELDCSR  0x09
  27
  28 /* Possible CPU types */
  29 #define XSCALE_IXP4XX_PXA2XX    0x0
  30 #define XSCALE_PXA3XX           0x4
  31
  32 enum xscale_debug_reason {
  33         XSCALE_DBG_REASON_GENERIC,
  34         XSCALE_DBG_REASON_RESET,
  35         XSCALE_DBG_REASON_TB_FULL,
  36 };
  37
  38 enum xscale_trace_entry_type {
  39         XSCALE_TRACE_MESSAGE = 0x0,
  40         XSCALE_TRACE_ADDRESS = 0x1,
  41 };
  42
  43 struct xscale_trace_entry {
  44         uint8_t data;
  45         enum xscale_trace_entry_type type;
  46 };
  47
  48 struct xscale_trace_data {
  49         struct xscale_trace_entry *entries;
  50         int depth;
  51         uint32_t chkpt0;
  52         uint32_t chkpt1;
  53         uint32_t last_instruction;
  54         unsigned int num_checkpoints;
  55         struct xscale_trace_data *next;
  56 };
  57
  58 enum trace_mode {
  59         XSCALE_TRACE_DISABLED,
  60         XSCALE_TRACE_FILL,
  61         XSCALE_TRACE_WRAP
  62 };
  63
  64 struct xscale_trace {
  65         struct image *image;                                    /* source for target opcodes */
  66         struct xscale_trace_data *data;         /* linked list of collected trace data */
  67         int buffer_fill;                                /* maximum number of trace runs to read */
  68         int fill_counter;                               /* running count during trace collection */
  69         enum trace_mode mode;
  70         enum arm_state core_state;      /* current core state (ARM, Thumb) */
  71 };
  72
  73 struct xscale_common {
  74         unsigned int common_magic;
  75
  76         /* armv4/5 common stuff */
  77         struct arm arm;
  78
  79         /* XScale registers (CP15, DBG) */
  80         struct reg_cache *reg_cache;
  81
  82         /* current state of the debug handler */
  83         uint32_t handler_address;
  84
  85         /* target-endian buffers with exception vectors */
  86         uint32_t low_vectors[8];
  87         uint32_t high_vectors[8];
  88
  89         /* static low vectors */
  90         uint8_t static_low_vectors_set; /* bit field with static vectors set by the user */
  91         uint8_t static_high_vectors_set; /* bit field with static vectors set by the user */
  92         uint32_t static_low_vectors[8];
  93         uint32_t static_high_vectors[8];
  94
  95         /* DCache cleaning */
  96         uint32_t cache_clean_address;
  97
  98         /* whether hold_rst and ext_dbg_break should be set */
  99         int hold_rst;
 100         int external_debug_break;
 101
 102         /* breakpoint / watchpoint handling */
 103         int dbr_available;
 104         int dbr0_used;
 105         int dbr1_used;
 106         int ibcr_available;
 107         int ibcr0_used;
 108         int     ibcr1_used;
 109         uint32_t arm_bkpt;
 110         uint16_t thumb_bkpt;
 111
 112         uint8_t vector_catch;
 113
 114         struct xscale_trace trace;
 115
 116         int arch_debug_reason;
 117
 118         /* MMU/Caches */
 119         struct armv4_5_mmu_common armv4_5_mmu;
 120         uint32_t cp15_control_reg;
 121
 122         int fast_memory_access;
 123
 124         /* CPU variant */
 125         int xscale_variant;
 126 };
 127
 128 static inline struct xscale_common *
 129 target_to_xscale(struct target *target)
 130 {
 131         return container_of(target->arch_info, struct xscale_common, arm);
 132 }
 133
 134 struct xscale_reg {
 135         int dbg_handler_number;
 136         struct target *target;
 137 };
 138
 139 enum {
 140         XSCALE_MAINID,          /* 0 */
 141         XSCALE_CACHETYPE,
 142         XSCALE_CTRL,
 143         XSCALE_AUXCTRL,
 144         XSCALE_TTB,
 145         XSCALE_DAC,
 146         XSCALE_FSR,
 147         XSCALE_FAR,
 148         XSCALE_PID,
 149         XSCALE_CPACCESS,
 150         XSCALE_IBCR0,           /* 10 */
 151         XSCALE_IBCR1,
 152         XSCALE_DBR0,
 153         XSCALE_DBR1,
 154         XSCALE_DBCON,
 155         XSCALE_TBREG,
 156         XSCALE_CHKPT0,
 157         XSCALE_CHKPT1,
 158         XSCALE_DCSR,
 159         XSCALE_TX,
 160         XSCALE_RX,                      /* 20 */
 161         XSCALE_TXRXCTRL,
 162 };
 163
 164 #define ERROR_XSCALE_NO_TRACE_DATA      (-700)
 165
 166 /* DCSR bit and field definitions */
 167 #define DCSR_TR (1 << 16)
 168 #define DCSR_TU (1 << 17)
 169 #define DCSR_TS (1 << 18)
 170 #define DCSR_TA (1 << 19)
 171 #define DCSR_TD (1 << 20)
 172 #define DCSR_TI (1 << 22)
 173 #define DCSR_TF (1 << 23)
 174 #define DCSR_TRAP_MASK \
 175         (DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
 176
 177 #endif /* OPENOCD_TARGET_XSCALE_H */