2 set RCC_CR
[expr $RCC_BASE + 0x00]
3 set RCC_CFGR
[expr $RCC_BASE + 0x04]
4 set RCC_CIR
[expr $RCC_BASE + 0x08]
5 set RCC_APB2RSTR
[expr $RCC_BASE + 0x0c]
6 set RCC_APB1RSTR
[expr $RCC_BASE + 0x10]
7 set RCC_AHBENR
[expr $RCC_BASE + 0x14]
8 set RCC_APB2ENR
[expr $RCC_BASE + 0x18]
9 set RCC_APB1ENR
[expr $RCC_BASE + 0x1c]
10 set RCC_BDCR
[expr $RCC_BASE + 0x20]
11 set RCC_CSR
[expr $RCC_BASE + 0x24]
14 proc show_RCC_CR
{ } {
15 if [ catch { set val
[show_mmr32_reg RCC_CR
] } msg
] {
19 show_mmr_bitfield
0 0 $val HSI
{ OFF ON
}
20 show_mmr_bitfield
1 1 $val HSIRDY
{ NOTRDY RDY
}
21 show_mmr_bitfield
7 3 $val HSITRIM
{ _NUMBER_
}
22 show_mmr_bitfield
15 8 $val HSICAL
{ _NUMBER_
}
23 show_mmr_bitfield
16 16 $val HSEON
{ OFF ON
}
24 show_mmr_bitfield
17 17 $val HSERDY
{ NOTRDY RDY
}
25 show_mmr_bitfield
18 18 $val HSEBYP
{ NOTBYPASSED BYPASSED
}
26 show_mmr_bitfield
19 19 $val CSSON
{ OFF ON
}
27 show_mmr_bitfield
24 24 $val PLLON
{ OFF ON
}
28 show_mmr_bitfield
25 25 $val PLLRDY
{ NOTRDY RDY
}
31 proc show_RCC_CFGR
{ } {
32 if [ catch { set val
[show_mmr32_reg RCC_CFGR
] } msg
] {
37 show_mmr_bitfield
1 0 $val SW
{ HSI HSE PLL ILLEGAL
}
38 show_mmr_bitfield
3 2 $val SWS
{ HSI HSE PLL ILLEGAL
}
39 show_mmr_bitfield
7 4 $val HPRE
{ sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512
}
40 show_mmr_bitfield
10 8 $val PPRE1
{ hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16
}
41 show_mmr_bitfield
13 11 $val PPRE2
{ hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16
}
42 show_mmr_bitfield
15 14 $val ADCPRE
{ pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16
}
43 show_mmr_bitfield
16 16 $val PLLSRC
{ HSI_div_2 HSE
}
44 show_mmr_bitfield
17 17 $val PLLXTPRE
{ hse_div1 hse_div2
}
45 show_mmr_bitfield
21 18 $val PLLMUL
{ x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16
}
46 show_mmr_bitfield
22 22 $val USBPRE
{ div1 div1_5
}
47 show_mmr_bitfield
26 24 $val MCO
{ none none none none SysClk HSI HSE PLL_div2
}
51 proc show_RCC_CIR
{ } {
52 if [ catch { set val
[show_mmr32_reg RCC_CIR
] } msg
] {
58 proc show_RCC_APB2RSTR
{ } {
59 if [ catch { set val
[ show_mmr32_reg RCC_APB2RSTR
] } msg
] {
62 for { set x
0 } { $x < 32 } { incr x
} {
81 show_mmr32_bits bits
$val
84 proc show_RCC_APB1RSTR
{ } {
85 if [ catch { set val
[ show_mmr32_reg RCC_APB1RSTR
] } msg
] {
120 show_mmr32_bits bits
$val
124 proc show_RCC_AHBENR
{ } {
125 if [ catch { set val
[ show_mmr32_reg RCC_AHBENR
] } msg
] {
160 show_mmr32_bits bits
$val
163 proc show_RCC_APB2ENR
{ } {
164 if [ catch { set val
[ show_mmr32_reg RCC_APB2ENR
] } msg
] {
199 show_mmr32_bits bits
$val
203 proc show_RCC_APB1ENR
{ } {
204 if [ catch { set val
[ show_mmr32_reg RCC_APB1ENR
] } msg
] {
239 show_mmr32_bits bits
$val
242 proc show_RCC_BDCR
{ } {
243 if [ catch { set val
[ show_mmr32_reg RCC_BDCR
] } msg
] {
246 for { set x
0 } { $x < 32 } { incr x
} {
256 show_mmr32_bits bits
$val
259 proc show_RCC_CSR
{ } {
260 if [ catch { set val
[ show_mmr32_reg RCC_CSR
] } msg
] {
263 for { set x
0 } { $x < 32 } { incr x
} {
275 show_mmr32_bits bits
$val
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