tcl/board/alphascale_asm9260_ek.cfg

   1 source [find target/alphascale_asm9260t.cfg]
   2
   3 reset_config trst_and_srst
   4
   5 $_TARGETNAME configure -event reset-init {
   6         echo "Configure clock"
   7         # Enable SRAM clk
   8         mww 0x80040024 0x4
   9         # Enable IRQ clk
  10         mww 0x80040034 0x100
  11         # Enable DMA0,1 clk
  12         mww 0x80040024 0x600
  13         # Make sysre syspll is enabled
  14         mww 0x80040238 0x750
  15         #CPU = PLLCLK/2
  16         mww 0x8004017C 0x2
  17         #SYSAHBCLK = CPUCLK/2
  18         mww 0x80040180 0x2
  19         # Set PLL freq to 480MHz
  20         mww 0x80040100 480
  21         # normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
  22         sleep 100
  23
  24         # select PLL as main source
  25         mww 0x80040120 0x1
  26         # disable and enble main clk to update changes?
  27         mww 0x80040124 0x0
  28         mww 0x80040124 0x1
  29
  30         echo "Configure memory"
  31         #enable EMI CLK
  32         mww 0x80040024 0x40
  33
  34         # configure memory controller for internal SRAM
  35         mww 0x80700000 0x1188
  36         # change default emi clk delay
  37         mww 0x8004034C 0xA0503
  38         # make sure chip_select_register2_low has correct value (why?)
  39         mww 0x8070001c 0x20000000
  40         # set type to sdram and size to 32MB
  41         mww 0x8070005c 0xa
  42         # configure internal SDRAM timing
  43         mww 0x80700004 0x024996d9
  44         # configure Static Memory timing
  45         mww 0x80700094 0x00542b4f
  46
  47         echo "Configure uart4"
  48         # enable pinctrl clk
  49         mww 0x80040024 0x2000000
  50         # mux GPIO3_0 and GPIO3_1 to UART4
  51         mww 0x80044060 0x2
  52         mww 0x80044064 0x2
  53         # configure UART4CLKDIV
  54         mww 0x800401a8 0x1
  55         # enable uart4 clk
  56         mww 0x80040024 0x8000
  57         # clear softrst and clkgate on uart4
  58         mww 0x80010008 0xC0000000
  59         # set bandrate 115200 12M
  60         mww 0x80010030 0x00062070
  61         # enable Rx&Tx
  62         mww 0x80010024 0x301
  63         # clear hw control
  64         mww 0x80010028 0xc000
  65 }
  66
  67 $_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
  68 $_TARGETNAME arm7_9 fast_memory_access enable
  69 $_TARGETNAME arm7_9 dcc_downloads enable