tcl/board/at91rm9200-ek.cfg

   1 #
   2 # Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   3 #
   4 # under GPLv2 Only
   5 #
   6 # This is for the "at91rm9200-ek" eval board.
   7 #
   8 #
   9 # It has atmel at91rm9200 chip.
  10 source [find target/at91rm9200.cfg]
  11
  12 reset_config trst_and_srst
  13
  14 $_TARGETNAME configure -event gdb-attach { reset init }
  15 $_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
  16
  17 ## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
  18 set _FLASHNAME $_CHIPNAME.flash
  19 flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
  20
  21 # The chip may run @ 32khz, so set a really low JTAG speed
  22 adapter_khz 8
  23
  24 proc at91rm9200_ek_init { } {
  25         # Try to run at 1khz... Yea, that slow!
  26         # Chip is really running @ 32khz
  27         adapter_khz 8
  28
  29         mww 0xfffffc64 0xffffffff
  30         ## disable all clocks but system clock
  31         mww 0xfffffc04 0xfffffffe
  32         ## disable all clocks to pioa and piob
  33         mww 0xfffffc14 0xffffffc3
  34         ## master clock = slow cpu = slow
  35         ## (means the CPU is running at 32khz!)
  36         mww 0xfffffc30 0
  37         ## main osc enable
  38         mww 0xfffffc20 0x0000ff01
  39         ## MC_PUP
  40         mww 0xFFFFFF50 0x00000000
  41         ## MC_PUER: Memory controller protection unit disable
  42         mww 0xFFFFFF54 0x00000000
  43         ## EBI_CFGR
  44         mww 0xFFFFFF64 0x00000000
  45         ## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
  46         mww 0xFFFFFF70 0x00003284
  47
  48         ## Init Clocks
  49         ## CKGR_PLLAR
  50         mww 0xFFFFFC28 0x2000BF05
  51         ## PLLAR: 179,712000 MHz for PCK
  52         mww 0xFFFFFC28 0x20263E04
  53         sleep 100
  54         ## PMC_MCKR
  55         mww 0xFFFFFC30 0x00000100
  56         sleep 100
  57         ## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
  58         mww 0xFFFFFC30 0x00000202
  59         sleep 100
  60
  61         #========================================
  62         # CPU now runs at 180mhz
  63         # SYS runs at 60mhz.
  64         adapter_khz 40000
  65         #========================================
  66
  67         ## Init SDRAM
  68         ## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
  69         mww 0xFFFFF870 0xFFFF0000
  70         ## PIOC_BSR:
  71         mww 0xFFFFF874 0x00000000
  72         ## PIOC_PDR:
  73         mww 0xFFFFF804 0xFFFF0000
  74         ## EBI_CSA : CS1=SDRAM
  75         mww 0xFFFFFF60 0x00000002
  76         ## EBI_CFGR:
  77         mww 0xFFFFFF64 0x00000000
  78         ## SDRC_CR :
  79         mww 0xFFFFFF98 0x2188c155
  80         ## SDRC_MR : Precharge All
  81         mww 0xFFFFFF90 0x00000002
  82         ## access SDRAM
  83         mww 0x20000000 0x00000000
  84         ## SDRC_MR : Refresh
  85         mww 0xFFFFFF90 0x00000004
  86         ## access SDRAM
  87         mww 0x20000000 0x00000000
  88         ## access SDRAM
  89         mww 0x20000000 0x00000000
  90         ## access SDRAM
  91         mww 0x20000000 0x00000000
  92         ## access SDRAM
  93         mww 0x20000000 0x00000000
  94         ## access SDRAM
  95         mww 0x20000000 0x00000000
  96         ## access SDRAM
  97         mww 0x20000000 0x00000000
  98         ## access SDRAM
  99         mww 0x20000000 0x00000000
 100         ## access SDRAM
 101         mww 0x20000000 0x00000000
 102         ## SDRC_MR : Load Mode Register
 103         mww 0xFFFFFF90 0x00000003
 104         ## access SDRAM
 105         mww 0x20000080 0x00000000
 106         ## SDRC_TR : Write refresh rate
 107         mww 0xFFFFFF94 0x000002E0
 108         ## access SDRAM
 109         mww 0x20000000 0x00000000
 110         ## SDRC_MR : Normal Mode
 111         mww 0xFFFFFF90 0x00000000
 112         ## access SDRAM
 113         mww 0x20000000 0x00000000
 114 }