tcl/board/at91sam9263-ek.cfg

   1 ################################################################################
   2 # Atmel AT91SAM9263-EK eval board
   3 ################################################################################
   4
   5 source [find mem_helper.tcl]
   6 source [find target/at91sam9263.cfg]
   7 uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
   8 uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
   9 uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
  10 uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
  11
  12 # By default S1 is open and this means that NTRST is not connected.
  13 # The reset_config in target/at91sam9263.cfg is overridden here.
  14 # (or S1 must be populated with a 0 Ohm resistor)
  15 reset_config srst_only
  16
  17 scan_chain
  18 $_TARGETNAME configure -event gdb-attach { reset init }
  19 $_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
  20 $_TARGETNAME configure -event reset-start { at91sam9_reset_start }
  21
  22 proc at91sam9263ek_reset_init { } {
  23
  24         set config(master_pll_div)      14
  25         set config(master_pll_mul)      171
  26
  27         set val [expr $::AT91_WDT_WDV]                  ;# Counter Value
  28         set val [expr ($val | $::AT91_WDT_WDDIS)]       ;# Watchdog Disable
  29         set val [expr ($val | $::AT91_WDT_WDD)]         ;# Delta Value
  30         set val [expr ($val | $::AT91_WDT_WDDBGHLT)]    ;# Debug Halt
  31         set val [expr ($val | $::AT91_WDT_WDIDLEHLT)]   ;# Idle Halt
  32
  33         set config(wdt_mr_val) $val
  34
  35         set config(sdram_piod) 1
  36         ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
  37         set config(matrix_ebicsa_addr)  $::AT91_MATRIX_EBI0CSA
  38
  39         set val [expr $::AT91_MATRIX_EBI0_DBPUC]
  40         set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
  41         set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
  42         set config(matrix_ebicsa_val) $val
  43
  44         ;# SDRAMC_CR - Configuration register
  45         set val [expr $::AT91_SDRAMC_NC_9]
  46         set val [expr ($val | $::AT91_SDRAMC_NR_13)]
  47         set val [expr ($val | $::AT91_SDRAMC_NB_4)]
  48         set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
  49         set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
  50         set val [expr ($val | (1 <<  8))]               ;# Write Recovery Delay
  51         set val [expr ($val | (7 << 12))]               ;# Row Cycle Delay
  52         set val [expr ($val | (2 << 16))]               ;# Row Precharge Delay
  53         set val [expr ($val | (2 << 20))]               ;# Row to Column Delay
  54         set val [expr ($val | (5 << 24))]               ;# Active to Precharge Delay
  55         set val [expr ($val | (1 << 28))]               ;# Exit Self Refresh to Active Delay
  56
  57         set config(sdram_cr_val) $val
  58
  59         set config(sdram_tr_val) 0x13c
  60
  61         set config(sdram_base) $::AT91_CHIPSELECT_1
  62         at91sam9_reset_init $config
  63 }