tcl/board/atmel_at91sam9260-ek.cfg

   1 ################################################################################
   2 # Atmel AT91SAM9260-EK eval board
   3 #
   4 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
   5 #
   6 # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
   7 #                     OSCSEL configured for external 32.768 kHz crystal
   8 #
   9 # 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
  10 #
  11 ################################################################################
  12
  13 # We add to the minimal configuration.
  14 source [find target/at91sam9260.cfg]
  15
  16 # By default S1 is open and this means that NTRST is not connected.
  17 # The reset_config in target/at91sam9260.cfg is overridden here.
  18 # (or S1 must be populated with a 0 Ohm resistor)
  19 reset_config srst_only
  20
  21 $_TARGETNAME configure -event reset-start {
  22         # At reset CPU runs at 32.768 kHz.
  23         # JTAG Frequency must be 6 times slower if RCLK is not supported.
  24         jtag_rclk 5
  25         halt
  26         # RSTC_MR : enable user reset, MMU may be enabled... use physical address
  27         arm926ejs mww_phys 0xfffffd08 0xa5000501
  28 }
  29
  30 $_TARGETNAME configure -event reset-init {
  31         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
  32
  33         mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
  34         sleep 20                          # wait 20 ms
  35         mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
  36         sleep 10                          # wait 10 ms
  37         mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
  38         sleep 20                          # wait 20 ms
  39         mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
  40         sleep 10                          # wait 10 ms
  41         mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
  42         sleep 10                          # wait 10 ms
  43
  44         # Increase JTAG Speed to 6 MHz if RCLK is not supported
  45         jtag_rclk 6000
  46
  47         arm7_9 dcc_downloads enable       # Enable faster DCC downloads
  48
  49         mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
  50         mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
  51
  52         mww 0xffffef1c 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
  53
  54         mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
  55
  56         mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
  57         mww 0x20000000 0
  58         mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
  59         mww 0x20000000 0
  60         mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  61         mww 0x20000000 0
  62         mww 0xffffea00 0x4
  63         mww 0x20000000 0
  64         mww 0xffffea00 0x4
  65         mww 0x20000000 0
  66         mww 0xffffea00 0x4
  67         mww 0x20000000 0
  68         mww 0xffffea00 0x4
  69         mww 0x20000000 0
  70         mww 0xffffea00 0x4
  71         mww 0x20000000 0
  72         mww 0xffffea00 0x4
  73         mww 0x20000000 0
  74         mww 0xffffea00 0x4
  75         mww 0x20000000 0
  76         mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
  77         mww 0x20000000 0
  78         mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
  79         mww 0x20000000 0
  80         mww 0xffffea04 0x2b6              # SDRAMC_TR : Set refresh timer count to 7us
  81 }