tcl/board/csb337.cfg

   1 # Cogent CSB337
   2 #   http://cogcomp.com/csb_csb337.htm
   3
   4 source [find target/at91rm9200.cfg]
   5
   6 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
   7 set _FLASHNAME $_CHIPNAME.flash
   8 flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
   9
  10 # ETM9 trace port connector present on this board, 16 data pins.
  11 if { [info exists ETM_DRIVER] } {
  12         etm config $_TARGETNAME 16 normal half $ETM_DRIVER
  13         # OpenOCD may someday support a real trace port driver...
  14         # system config file would need to configure it.
  15 } else {
  16         etm config $_TARGETNAME 16 normal half dummy
  17         etm_dummy config $_TARGETNAME
  18 }
  19
  20 proc csb337_clk_init { } {
  21         # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
  22         jtag_khz 8
  23
  24         # CKGR_MOR:  start main oscillator (3.6864 MHz)
  25         mww 0xfffffc20 0xff01
  26         sleep 10
  27
  28         # CKGR_PLLAR:  start PLL A for CPU and peripherals (184.32 MHz)
  29         mww 0xfffffc28 0x20313e01
  30         # CKGR_PLLBR:  start PLL B for USB timing (96 MHz, with div2)
  31         mww 0xfffffc2c 0x12703e18
  32         # let PLLs lock
  33         sleep 10
  34
  35         # PMC_MCKR:  switch to CPU clock = PLLA, master clock = CPU/4
  36         mww 0xfffffc30 0x0302
  37         sleep 20
  38
  39         # CPU is in Normal Mode ... allows faster JTAG clock speed
  40         jtag_khz 40000
  41 }
  42
  43 proc csb337_nor_init { } {
  44         # SMC_CSR0:  adjust timings (10 wait states)
  45         mww 0xffffff70 0x1100318a
  46
  47         flash probe 0
  48 }
  49
  50 proc csb337_sdram_init { } {
  51         # enable PIOC clock
  52         mww 0xfffffc10 0x0010
  53         # PC31..PC16 are D31..D16, with internal pullups like D15..D0
  54         mww 0xfffff870 0xffff0000
  55         mww 0xfffff874 0x0
  56         mww 0xfffff804 0xffff0000
  57
  58         # SDRC_CR: set timings
  59         mww 0xffffff98 0x2188b0d5
  60
  61         # SDRC_MR: issue all banks precharge to SDRAM
  62         mww 0xffffff90 2
  63         mww 0x20000000 0
  64
  65         # SDRC_MR: 8 autorefresh cycles
  66         mww 0xffffff90 4
  67         mww 0x20000000 0
  68         mww 0x20000000 0
  69         mww 0x20000000 0
  70         mww 0x20000000 0
  71         mww 0x20000000 0
  72         mww 0x20000000 0
  73         mww 0x20000000 0
  74         mww 0x20000000 0
  75
  76         # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
  77         mww 0xffffff90 3
  78         mww 0x20000080 0
  79
  80         # SDRC_TR: set refresh rate
  81         mww 0xffffff94 0x200
  82         mww 0x20000000 0
  83
  84         # SDRC_MR: normal mode, 32 bit bus
  85         mww 0xffffff90 0
  86         mww 0x20000000 0
  87 }
  88
  89 # The rm9200 chip has just been reset.  Bring it up far enough
  90 # that we can write flash or run code from SDRAM.
  91 proc csb337_reset_init { } {
  92         csb337_clk_init
  93
  94         # EBI_CSA:  CS0 = NOR, CS1 = SDRAM
  95         mww 0xffffff60 0x02
  96
  97         csb337_nor_init
  98         csb337_sdram_init
  99
 100         # Update CP15 control register ... we don't seem to be able to
 101         # read/modify/write its value through a TCL variable, so just
 102         # write it.  Fields are zero unless listed here ... and note
 103         # that OpenOCD numbers this register "2", not "1" (!).
 104         #
 105         #  - Core to use Async Clocking mode (so it uses 184 MHz most
 106         #    of the time instead of limiting to the master clock rate):
 107         #       iA(31) = 1, nF(30) = 1
 108         #  - Icache on (it's disabled now, slowing i-fetches)
 109         #       I(12) = 1
 110         #  - Reserved/ones
 111         #       6:3 = 1
 112         arm920t cp15 2 0xc0001078
 113 }
 114
 115 $_TARGETNAME configure -event reset-init {csb337_reset_init}