tcl/board/csb337.cfg

   1 # Cogent CSB337
   2 #   http://cogcomp.com/csb_csb337.htm
   3
   4 source [find target/at91rm9200.cfg]
   5
   6 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
   7 flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
   8
   9 # ETM9 trace port connector present on this board, 16 data pins.
  10 if { [info exists ETM_DRIVER] } {
  11         etm config $_TARGETNAME 16 normal half $ETM_DRIVER
  12         # OpenOCD may someday support a real trace port driver...
  13         # system config file would need to configure it.
  14 } else {
  15         etm config $_TARGETNAME 16 normal half dummy
  16         etm_dummy config $_TARGETNAME
  17 }
  18
  19 proc csb337_clk_init { } {
  20         # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
  21         jtag_khz 8
  22
  23         # CKGR_MOR:  start main oscillator (3.6864 MHz)
  24         mww 0xfffffc20 0xff01
  25         sleep 10
  26
  27         # CKGR_PLLAR:  start PLL A for CPU and peripherals (184.32 MHz)
  28         mww 0xfffffc28 0x20313e01
  29         # CKGR_PLLBR:  start PLL B for USB timing (96 MHz, with div2)
  30         mww 0xfffffc2c 0x12703e18
  31         # let PLLs lock
  32         sleep 10
  33
  34         # PMC_MCKR:  switch to CPU clock = PLLA, master clock = CPU/4
  35         mww 0xfffffc30 0x0302
  36         sleep 20
  37
  38         # CPU is in Normal Mode ... allows faster JTAG clock speed
  39         jtag_khz 40000
  40 }
  41
  42 proc csb337_nor_init { } {
  43         # SMC_CSR0:  adjust timings (10 wait states)
  44         mww 0xffffff70 0x1100318a
  45
  46         flash probe 0
  47 }
  48
  49 proc csb337_sdram_init { } {
  50         # enable PIOC clock
  51         mww 0xfffffc10 0x0010
  52         # PC31..PC16 are D31..D16, with internal pullups like D15..D0
  53         mww 0xfffff870 0xffff0000
  54         mww 0xfffff874 0x0
  55         mww 0xfffff804 0xffff0000
  56
  57         # SDRC_CR: set timings
  58         mww 0xffffff98 0x2188b0d5
  59
  60         # SDRC_MR: issue all banks precharge to SDRAM
  61         mww 0xffffff90 2
  62         mww 0x20000000 0
  63
  64         # SDRC_MR: 8 autorefresh cycles
  65         mww 0xffffff90 4
  66         mww 0x20000000 0
  67         mww 0x20000000 0
  68         mww 0x20000000 0
  69         mww 0x20000000 0
  70         mww 0x20000000 0
  71         mww 0x20000000 0
  72         mww 0x20000000 0
  73         mww 0x20000000 0
  74
  75         # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
  76         mww 0xffffff90 3
  77         mww 0x20000080 0
  78
  79         # SDRC_TR: set refresh rate
  80         mww 0xffffff94 0x200
  81         mww 0x20000000 0
  82
  83         # SDRC_MR: normal mode, 32 bit bus
  84         mww 0xffffff90 0
  85         mww 0x20000000 0
  86 }
  87
  88 # The rm9200 chip has just been reset.  Bring it up far enough
  89 # that we can write flash or run code from SDRAM.
  90 proc csb337_reset_init { } {
  91         csb337_clk_init
  92
  93         # EBI_CSA:  CS0 = NOR, CS1 = SDRAM
  94         mww 0xffffff60 0x02
  95
  96         csb337_nor_init
  97         csb337_sdram_init
  98
  99         # Update CP15 control register ... we don't seem to be able to
 100         # read/modify/write its value through a TCL variable, so just
 101         # write it.  Fields are zero unless listed here ... and note
 102         # that OpenOCD numbers this register "2", not "1" (!).
 103         #
 104         #  - Core to use Async Clocking mode (so it uses 184 MHz most
 105         #    of the time instead of limiting to the master clock rate):
 106         #       iA(31) = 1, nF(30) = 1
 107         #  - Icache on (it's disabled now, slowing i-fetches)
 108         #       I(12) = 1
 109         #  - Reserved/ones
 110         #       6:3 = 1
 111         arm920t cp15 2 0xc0001078
 112 }
 113
 114 $_TARGETNAME configure -event reset-init {csb337_reset_init}