tcl/board/csb732.cfg

   1 # The Cogent CSB732 board has a single i.MX35 chip
   2 source [find target/imx35.cfg]
   3
   4 # Determined by trial and error
   5 reset_config trst_and_srst combined
   6 adapter_nsrst_delay 200
   7 jtag_ntrst_delay 200
   8
   9 $_TARGETNAME configure -event gdb-attach { reset init }
  10 $_TARGETNAME configure -event reset-init { csb732_init }
  11
  12 # Bare-bones initialization of core clocks and SDRAM
  13 proc csb732_init { } {
  14
  15         # Disable fast writing only for init
  16         memwrite burst disable
  17
  18         # All delay loops are omitted.
  19         # We assume the interpreter latency is enough.
  20
  21         # Allow access to all coprocessors
  22         arm mcr 15 0 15 1 0 0x2001
  23
  24         # Disable MMU, caches, write buffer
  25         arm mcr 15 0 1 0 0 0x78
  26
  27         # Grant manager access to all domains
  28         arm mcr 15 0 3 0 0 0xFFFFFFFF
  29
  30         # Set ARM clock to 532 MHz, AHB to 133 MHz
  31         mww 0x53F80004 0x1000
  32
  33         # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
  34         mww 0x53F8001C 0xB2C01
  35
  36         set ESDMISC 0xB8001010
  37         set ESDCFG0 0xB8001004
  38         set ESDCTL0 0xB8001000
  39
  40         # Enable DDR
  41         mww $ESDMISC 0x4
  42
  43         # Timing
  44         mww $ESDCFG0 0x007fff3f
  45
  46         # CS0
  47         mww $ESDCTL0 0x92120080
  48
  49         # Precharge all dummy write
  50         mww 0x80000400 0
  51
  52         # Enable CS) auto-refresh
  53         mww $ESDCTL0 0xA2120080
  54
  55         # Refresh twice (dummy writes)
  56         mww 0x80000000 0
  57         mww 0x80000000 0
  58
  59         # Enable CS0 load mode register
  60         mww $ESDCTL0 0xB2120080
  61
  62         # Dummy writes
  63         mwb 0x80000033 0x01
  64         mwb 0x81000000 0x01
  65
  66         mww $ESDCTL0 0x82226080
  67         mww 0x80000000 0
  68
  69         # Re-enable fast writing
  70         memwrite burst enable
  71 }