tcl/board/digi_connectcore_wi-9c.cfg

   1 ######################################
   2 # Target: DIGI ConnectCore Wi-9C
   3 ######################################
   4
   5 reset_config trst_and_srst
   6
   7 if { [info exists CHIPNAME] } {
   8    set  _CHIPNAME $CHIPNAME
   9 } else {
  10    set  _CHIPNAME ns9360
  11 }
  12
  13 if { [info exists ENDIAN] } {
  14    set  _ENDIAN $ENDIAN
  15 } else {
  16   # This config file was defaulting to big endian..
  17    set  _ENDIAN big
  18 }
  19
  20
  21 # What's a good fallback frequency for this board if RCLK is
  22 # not available??
  23 jtag_rclk 1000
  24
  25
  26 if { [info exists CPUTAPID ] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    set _CPUTAPID 0xFFFFFFFF
  30 }
  31
  32 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
  33 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  34
  35 jtag_nsrst_delay 200
  36 jtag_ntrst_delay 0
  37
  38
  39 ######################
  40 # Target configuration
  41 ######################
  42
  43 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
  44 $_TARGETNAME configure -event reset-init {
  45         mww 0x90600104 0x33313333
  46         mww 0xA0700000 0x00000001  # Enable the memory controller.
  47         mww 0xA0700024 0x00000006  # Set the refresh counter 6
  48         mww 0xA0700028 0x00000001  #
  49         mww 0xA0700030 0x00000001  # Set the precharge period
  50         mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles
  51         mww 0xA070003C 0x00000001  # tAPR
  52         mww 0xA0700040 0x00000005  # tDAL
  53         mww 0xA0700044 0x00000001  # tWR
  54         mww 0xA0700048 0x00000006  # tRC 32 clock cycles
  55         mww 0xA070004C 0x00000006  # tRFC 32 clock cycles
  56         mww 0xA0700054 0x00000001  # tRRD
  57         mww 0xA0700058 0x00000001  # tMRD
  58         mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4)
  59         mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)
  60         mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)
  61         mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)
  62         #
  63         mww 0xA0700104 0x00000203  # CAS latency is 2 at 100 MHz
  64         mww 0xA0700124 0x00000203  # CAS latency is 2 at 100 MHz
  65         mww 0xA0700144 0x00000203  # CAS latency is 2 at 100 MHz
  66         mww 0xA0700164 0x00000203  # CAS latency is 2 at 100 MHz
  67         #
  68         mww 0xA0700020 0x00000103  # issue SDRAM PALL command
  69         #
  70         mww 0xA0700024 0x00000001  # Set the refresh counter to be as small as possible
  71         #
  72         # Add some dummy writes to give the SDRAM time to settle, it needs two
  73         # AHB clock cycles, here we poke in the debugger flag, this lets
  74         # the software know that we are in the debugger
  75         mww 0xA0900000 0x00000002
  76         mww 0xA0900000 0x00000002
  77         mww 0xA0900000 0x00000002
  78         mww 0xA0900000 0x00000002
  79         mww 0xA0900000 0x00000002
  80         #
  81         mdw 0xA0900000
  82         mdw 0xA0900000
  83         mdw 0xA0900000
  84         mdw 0xA0900000
  85         mdw 0xA0900000
  86         #
  87         mww 0xA0700024 0x00000030 # Set the refresh counter to 30
  88         mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
  89         #
  90         # Next we perform a read of RAM.
  91         # mw = move word.
  92         mdw 0x00022000
  93         # mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
  94         #
  95         mww 0xA0700020 0x00000003   # issue SDRAM NORMAL command
  96         mww 0xA0700100 0x00084280   # Enable buffer access
  97         mww 0xA0700120 0x00084280   # Enable buffer access
  98         mww 0xA0700140 0x00084280   # Enable buffer access
  99         mww 0xA0700160 0x00084280   # Enable buffer access
 100
 101         #Set byte lane state (static mem 1)"
 102         mww 0xA0700220, 0x00000082
 103         #Flash Start
 104         mww 0xA09001F8, 0x50000000
 105         #Flash Mask Reg
 106         mww 0xA09001FC, 0xFF000001
 107         mww 0xA0700028, 0x00000001
 108
 109         #  RAMAddr = 0x00020000
 110         #  RAMSize = 0x00004000
 111
 112         # Set the processor mode
 113         reg cpsr 0xd3
 114 }
 115
 116 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
 117
 118 #####################
 119 # Flash configuration
 120 #####################
 121
 122 #M29DW323DB - not working
 123 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
 124 flash bank cfi 0x50000000 0x0400000 2 2 0
 125
 126
 127