tcl/board/dm355evm.cfg

   1 # DM355 EVM board
   2 #   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
   3 #   http://c6000.spectrumdigital.com/evmdm355/
   4
   5 source [find target/ti_dm355.cfg]
   6
   7 reset_config trst_and_srst separate
   8
   9 # NOTE:  disable or replace this call to dm355evm_init if you're
  10 # debugging new UBL code from SRAM.
  11 $_TARGETNAME configure -event reset-init { dm355evm_init }
  12
  13 #
  14 # This post-reset init is called when the MMU isn't active, all IRQs
  15 # are disabled, etc.  It should do most of what a UBL does, except for
  16 # loading code (like U-Boot) into DRAM and running it.
  17 #
  18 proc dm355evm_init {} {
  19         global dm355
  20
  21         echo "Initialize DM355 EVM board"
  22
  23         # CLKIN = 24 MHz ... can't talk quickly to ARM yet
  24         jtag_rclk 1500
  25
  26         ########################
  27         # PLL1          = 432 MHz (/8, x144)
  28         # ...SYSCLK1    = 216 MHz (/2)  ... ARM, MJCP
  29         # ...SYSCLK2    = 108 MHz (/4)  ... Peripherals
  30         # ...SYSCLK3    = 27  MHz (/16) ... VPBE, DAC
  31         # ...SYSCLK4    = 108 MHz (/4)  ... VPSS
  32         #       pll1.{prediv,div1,div2} are fixed
  33         #       pll1.postdiv set in MISC (for *this* speed grade)
  34
  35         set addr [dict get $dm355 pllc1]
  36         set pll_divs [dict create]
  37         dict set pll_divs div3 16
  38         dict set pll_divs div4 4
  39         pll_v02_setup $addr 144 $pll_divs
  40
  41         # ARM is now running at 216 MHz, so JTAG can go faster
  42         jtag_rclk 20000
  43
  44         ########################
  45         # PLL2          = 342 MHz (/8, x114)
  46         # ....SYSCLK1   = 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
  47         #       pll2.{postdiv,div1} are fixed
  48
  49         set addr [dict get $dm355 pllc2]
  50         set pll_divs [dict create]
  51         dict set pll_divs div1 1
  52         dict set pll_divs prediv 8
  53         pll_v02_setup $addr 114 $pll_divs
  54
  55         ########################
  56         # PINMUX
  57
  58         # All Video Inputs
  59         davinci_pinmux $dm355 0 0x00007f55
  60         # All Video Outputs
  61         davinci_pinmux $dm355 1 0x00145555
  62         # EMIFA (NOTE: more could be set up for use as GPIOs)
  63         davinci_pinmux $dm355 2 0x00000c08
  64         # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
  65         davinci_pinmux $dm355 3 0x1bff55ff
  66         # MMC/SD0 instead of MS; SPI0
  67         davinci_pinmux $dm355 4 0x00000000
  68
  69         ########################
  70         # PSC setup (minimal)
  71
  72         # DDR EMIF/13, AEMIF/14, UART0/19
  73         psc_enable 13
  74         psc_enable 14
  75         psc_enable 19
  76         psc_go
  77
  78         ########################
  79         # DDR2 EMIF
  80
  81         # VTPIOCR impedance calibration
  82         set addr [dict get $dm355 sysbase]
  83         set addr [expr $addr + 0x70]
  84
  85         # clear CLR, LOCK, PWRDN; wait a clock; set CLR
  86         mmw $addr 0 0x20c0
  87         mmw $addr 0x2000 0
  88
  89         # wait for READY
  90         while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }
  91
  92         # set IO_READY; then LOCK and PWRSAVE; then PWRDN
  93         mmw $addr 0x4000 0
  94         mmw $addr 0x0180 0
  95         mmw $addr 0x0040 0
  96
  97         # NOTE:  this DDR2 initialization sequence borrows from
  98         # both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
  99
 100         # reset (then re-enable) DDR controller
 101         psc_reset 13
 102         psc_go
 103         psc_enable 13
 104         psc_go
 105
 106         # now set it up for Micron MT47H64M16HR-37E @ 171 MHz
 107
 108         set addr [dict get $dm355 ddr_emif]
 109
 110         # DDRPHYCR1
 111         mww [expr $addr + 0xe4] 0x50006404
 112
 113         # PBBPR -- burst priority
 114         mww [expr $addr + 0x20] 0xfe
 115
 116         # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
 117         mmw [expr $addr + 0x08] 0x00800000 0
 118         mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
 119
 120         # SDTIMR0, SDTIMR1
 121         mww [expr $addr + 0x10] 0x2a923249
 122         mww [expr $addr + 0x14] 0x4c17c763
 123
 124         # SDCR -- relock SDTIM*
 125         mmw [expr $addr + 0x08] 0 0x00008000
 126
 127         # SDRCR -- refresh rate (171 MHz * 7.8usec)
 128         mww [expr $addr + 0x0c] 1336
 129
 130         ########################
 131         # ASYNC EMIF
 132
 133         set addr [dict get $dm355 a_emif]
 134
 135         # slow/pessimistic timings
 136         set nand_timings 0x40400204
 137         # fast (25% faster page reads)
 138         #set nand_timings 0x0400008c
 139
 140         # AWCCR
 141         mww [expr $addr + 0x04] 0xff
 142         # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
 143         mww [expr $addr + 0x10] $nand_timings
 144         # CS1 == dm9000 Ethernet
 145         mww [expr $addr + 0x14] 0x00a00505
 146         # NANDFCR -- only CS0 has NAND
 147         mww [expr $addr + 0x60] 0x01
 148
 149         # default: both chipselects to the NAND socket are used
 150         nand probe 0
 151         nand probe 1
 152
 153         ########################
 154         # UART0
 155
 156         set addr [dict get $dm355 uart0]
 157
 158         # PWREMU_MGNT -- rx + tx in reset
 159         mww [expr $addr + 0x30] 0
 160
 161         # DLL, DLH -- 115200 baud
 162         mwb [expr $addr + 0x20] 0x0d
 163         mwb [expr $addr + 0x24] 0x00
 164
 165         # FCR - clear and disable FIFOs
 166         mwb [expr $addr + 0x08] 0x07
 167         mwb [expr $addr + 0x08] 0x00
 168
 169         # IER - disable IRQs
 170         mwb [expr $addr + 0x04] 0x00
 171
 172         # LCR - 8-N-1
 173         mwb [expr $addr + 0x0c] 0x03
 174
 175         # MCR - no flow control or loopback
 176         mwb [expr $addr + 0x10] 0x00
 177
 178         # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
 179         mww [expr $addr + 0x30] 0xe001
 180
 181
 182         ########################
 183
 184         # turn on icache - set I bit in cp15 register c1
 185         arm mcr 15 0 0 1 0 0x00051078
 186 }
 187
 188 # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
 189 #
 190 # NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
 191 # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
 192 # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
 193 # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
 194 set _FLASHNAME $_CHIPNAME.boot
 195 nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
 196 set _FLASHNAME $_CHIPNAME.flash
 197 nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
 198
 199 # FIXME
 200 #  - support writing UBL with its header (new layout only with new ROMs)
 201 #  - support writing ABL/U-Boot with its header (new layout)