tcl/board/embedded-artists_lpc2478-32.cfg

   1 # Embedded Artists eval board for LPC2478
   2 # http://www.embeddedartists.com/
   3
   4 # Delays on reset lines
   5 adapter_nsrst_delay 500
   6 jtag_ntrst_delay 1
   7
   8 # Adaptive JTAG clocking through RTCK.
   9 #
  10 jtag_rclk 20
  11
  12 # Target device: LPC2478
  13 set CCLK 72000
  14 source [find target/lpc2478.cfg]
  15
  16 # A working area will help speeding the flash programming
  17 $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
  18
  19 # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
  20 flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
  21
  22 # Helper
  23 #
  24 proc read_register {register} {
  25     set result ""
  26     mem2array result 32 $register 1
  27     return $result(0)
  28 }
  29
  30
  31 # Enable the PLL.
  32 # Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
  33 # Note: The PLL output runs at a frequency N times the desired CPU clock.
  34 #       It in unavoidable that the CPU clock drops down to (4 MHz/N) during
  35 #       the initialization!
  36 #       Here: N=4
  37 #       Note that if the PLL is already active at the time this script is
  38 #       called, the effective value of N is the value of CCLKCFG at that time!
  39 #
  40 proc enable_pll {} {
  41     # Disconnect PLL in case it is already connected
  42     if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
  43         # Disconnect it, but leave it enabled
  44         # (This MUST be done in two steps)
  45         mww 0xE01FC080 0x00000001       # PLLCON: disconnect PLL
  46         mww 0xE01FC08C 0x000000AA       # PLLFEED
  47         mww 0xE01FC08C 0x00000055       # PLLFEED
  48     }
  49     # Disable PLL (as it might already be enabled at this time!)
  50     mww 0xE01FC080 0x00000000       # PLLCON: disable PLL
  51     mww 0xE01FC08C 0x000000AA       # PLLFEED
  52     mww 0xE01FC08C 0x00000055       # PLLFEED
  53
  54     # Setup PLL to generate 288 MHz from internal RC oscillator
  55     mww 0xE01FC10C 0x00000000       # CLKSRCSEL: IRC
  56     mww 0xE01FC084 0x00000023       # PLLCFG: N=1, M=36
  57     mww 0xE01FC08C 0x000000AA       # PLLFEED
  58     mww 0xE01FC08C 0x00000055       # PLLFEED
  59     mww 0xE01FC080 0x00000001       # PLLCON: enable PLL
  60     mww 0xE01FC08C 0x000000AA       # PLLFEED
  61     mww 0xE01FC08C 0x00000055       # PLLFEED
  62     sleep 100
  63     mww 0xE01FC104 0x00000003       # CCLKCFG: divide by 4 (72 MHz)
  64     mww 0xE01FC080 0x00000003       # PLLCON: connect PLL
  65     mww 0xE01FC08C 0x000000AA       # PLLFEED
  66     mww 0xE01FC08C 0x00000055       # PLLFEED
  67 }
  68
  69
  70 # Event handlers
  71 #
  72 $_TARGETNAME configure -event reset-start {
  73     # Back to the slow JTAG clock
  74     jtag_rclk 20
  75 }
  76
  77
  78 $_TARGETNAME configure -event reset-init {
  79
  80     arm core_state arm
  81     arm7_9 dcc_downloads enable     # Speed up downloads by using DCC transfer
  82     arm7_9 fast_memory_access enable
  83
  84     # Peripheral clocks
  85     mww 0xE01FC0C4 0x04280FFE       # PCONP: (reset value)
  86
  87     # Map the user flash to the vector table area (0x00...0x3F)
  88     mww 0xE01FC040 0x00000001       # MEMMAP: User flash
  89
  90     # Memory accelerator module
  91     mww 0xE01FC004 0x00000003       # MAMTIM: 3 clock cycles
  92     mww 0xE01FC000 0x00000002       # MAMCR: fully enabled
  93
  94     # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
  95     mww 0xE002C014 0x55010115       # PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
  96                                     # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
  97                                     # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
  98     mww 0xE002C018 0x55555555       # PINSEL6: P3.0...P3.15=D0...D15
  99     mww 0xE002C01C 0x55555555       # PINSEL7: P3.16...P3.31=D16...D31
 100     mww 0xE002C020 0x55555555       # PINSEL8: P4.0...P4.15=A0...A15
 101     mww 0xE002C024 0x50051555       # PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
 102                                     # P4.25=WE, P4.30=CS0, P4.31=CS1
 103     mww 0xFFE08000 0x00000001       # EMCControl: Enable EMC
 104
 105     # Start PLL, then use faster JTAG clock
 106     enable_pll
 107     jtag_rclk 3000
 108
 109     # 16-bit flash @ CS0 (SST39VF3201-70)
 110     mww 0xFFE08200 0x00080081       # EMCStaticConfig0: 16 bit, PB=1, buffers on
 111     mww 0xFFE08204 0x00000000       # EMCStaticWaitWen0
 112     mww 0xFFE08208 0x00000000       # EMCStaticWaitOen0
 113     mww 0xFFE0820C 0x00000005       # EMCStaticWaitRd0
 114     mww 0xFFE08210 0x00000005       # EMCStaticWaitPage0
 115     mww 0xFFE08214 0x00000003       # EMCStaticWaitWr0
 116     mww 0xFFE08218 0x00000001       # EMCStaticWaitTurn0
 117
 118     # 8-bit NAND @ CS1
 119     # TODO
 120
 121     # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
 122     mww 0xFFE08028 0x00000001       # EMCDynamicReadConfig
 123     mww 0xFFE08030 0x00000001       # EMCDynamicRP
 124     mww 0xFFE08034 0x00000003       # EMCDynamicRAS
 125     mww 0xFFE08038 0x00000005       # EMCDynamicSREX
 126     mww 0xFFE0803C 0x00000001       # EMCDynamicAPR
 127     mww 0xFFE08040 0x00000005       # EMCDynamicDAL
 128     mww 0xFFE08044 0x00000001       # EMCDynamicWR
 129     mww 0xFFE08048 0x00000005       # EMCDynamicRC
 130     mww 0xFFE0804C 0x00000005       # EMCDynamicRFC
 131     mww 0xFFE08050 0x00000005       # EMCDynamicXSR
 132     mww 0xFFE08054 0x00000001       # EMCDynamicRRD
 133     mww 0xFFE08058 0x00000001       # EMCDynamicMRD
 134     #
 135     mww 0xFFE08104 0x00000202       # EMCDynamicRasCas0
 136     mww 0xFFE08100 0x00005488       # EMCDynamicConfig0
 137     sleep 100
 138     mww 0xFFE08020 0x00000183       # EMCDynamicControl: Clock on continuously, NOP
 139     sleep 10
 140     mww 0xFFE08020 0x00000103       # EMCDynamicControl: PRECHARGE-ALL
 141     mww 0xFFE08024 0x00000046       # EMCDynamicRefresh
 142     sleep 100
 143     mww 0xFFE08020 0x00000083       # EMCDynamicControl: MODE
 144     mdw 0xA0011000 1                # Set SDRAM mode register
 145     mww 0xFFE08020 0x00000000       # EMCDynamicControl: NORMAL
 146     mww 0xFFE08100 0x00085488       # EMCDynamicConfig0: Enable buffers
 147 }
 148