tcl/board/embedded-artists_lpc2478-32.cfg

   1 # Embedded Artists eval board for LPC2478
   2 # http://www.embeddedartists.com/
   3
   4 # Target device: LPC2478
   5 set CCLK 72000
   6 source [find target/lpc2478.cfg]
   7
   8 # Helper
   9 #
  10 proc read_register {register} {
  11     set result ""
  12     mem2array result 32 $register 1
  13     return $result(0)
  14 }
  15
  16 proc init_board {} {
  17     # Delays on reset lines
  18     adapter_nsrst_delay 500
  19     jtag_ntrst_delay 1
  20
  21     # Adaptive JTAG clocking through RTCK.
  22     #
  23     jtag_rclk 20
  24
  25     global _TARGETNAME
  26     global _CHIPNAME
  27
  28     # A working area will help speeding the flash programming
  29     $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
  30
  31     # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
  32     flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
  33
  34     # Event handlers
  35     #
  36     $_TARGETNAME configure -event reset-start {
  37         # Back to the slow JTAG clock
  38         jtag_rclk 20
  39     }
  40
  41     $_TARGETNAME configure -event reset-init {
  42         arm core_state arm
  43         arm7_9 dcc_downloads enable     ;# Speed up downloads by using DCC transfer
  44         arm7_9 fast_memory_access enable
  45
  46         # Peripheral clocks
  47         mww 0xE01FC0C4 0x04280FFE       ;# PCONP: (reset value)
  48
  49         # Map the user flash to the vector table area (0x00...0x3F)
  50         mww 0xE01FC040 0x00000001       ;# MEMMAP: User flash
  51
  52         # Memory accelerator module
  53         mww 0xE01FC004 0x00000003       ;# MAMTIM: 3 clock cycles
  54         mww 0xE01FC000 0x00000002       ;# MAMCR: fully enabled
  55
  56         # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
  57         mww 0xE002C014 0x55010115       ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
  58                                          # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
  59                                          # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
  60         mww 0xE002C018 0x55555555       ;# PINSEL6: P3.0...P3.15=D0...D15
  61         mww 0xE002C01C 0x55555555       ;# PINSEL7: P3.16...P3.31=D16...D31
  62         mww 0xE002C020 0x55555555       ;# PINSEL8: P4.0...P4.15=A0...A15
  63         mww 0xE002C024 0x50051555       ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
  64                                          # P4.25=WE, P4.30=CS0, P4.31=CS1
  65         mww 0xFFE08000 0x00000001       ;# EMCControl: Enable EMC
  66
  67         # Start PLL, then use faster JTAG clock
  68         enable_pll
  69         jtag_rclk 3000
  70
  71         # 16-bit flash @ CS0 (SST39VF3201-70)
  72         mww 0xFFE08200 0x00080081       ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
  73         mww 0xFFE08204 0x00000000       ;# EMCStaticWaitWen0
  74         mww 0xFFE08208 0x00000000       ;# EMCStaticWaitOen0
  75         mww 0xFFE0820C 0x00000005       ;# EMCStaticWaitRd0
  76         mww 0xFFE08210 0x00000005       ;# EMCStaticWaitPage0
  77         mww 0xFFE08214 0x00000003       ;# EMCStaticWaitWr0
  78         mww 0xFFE08218 0x00000001       ;# EMCStaticWaitTurn0
  79
  80         # 8-bit NAND @ CS1
  81         # TODO
  82
  83         # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
  84         mww 0xFFE08028 0x00000001       ;# EMCDynamicReadConfig
  85         mww 0xFFE08030 0x00000001       ;# EMCDynamicRP
  86         mww 0xFFE08034 0x00000003       ;# EMCDynamicRAS
  87         mww 0xFFE08038 0x00000005       ;# EMCDynamicSREX
  88         mww 0xFFE0803C 0x00000001       ;# EMCDynamicAPR
  89         mww 0xFFE08040 0x00000005       ;# EMCDynamicDAL
  90         mww 0xFFE08044 0x00000001       ;# EMCDynamicWR
  91         mww 0xFFE08048 0x00000005       ;# EMCDynamicRC
  92         mww 0xFFE0804C 0x00000005       ;# EMCDynamicRFC
  93         mww 0xFFE08050 0x00000005       ;# EMCDynamicXSR
  94         mww 0xFFE08054 0x00000001       ;# EMCDynamicRRD
  95         mww 0xFFE08058 0x00000001       ;# EMCDynamicMRD
  96         #
  97         mww 0xFFE08104 0x00000202       ;# EMCDynamicRasCas0
  98         mww 0xFFE08100 0x00005488       ;# EMCDynamicConfig0
  99         sleep 100
 100         mww 0xFFE08020 0x00000183       ;# EMCDynamicControl: Clock on continuously, NOP
 101         sleep 10
 102         mww 0xFFE08020 0x00000103       ;# EMCDynamicControl: PRECHARGE-ALL
 103         mww 0xFFE08024 0x00000046       ;# EMCDynamicRefresh
 104         sleep 100
 105         mww 0xFFE08020 0x00000083       ;# EMCDynamicControl: MODE
 106         mdw 0xA0011000 1                ;# Set SDRAM mode register
 107         mww 0xFFE08020 0x00000000       ;# EMCDynamicControl: NORMAL
 108         mww 0xFFE08100 0x00085488       ;# EMCDynamicConfig0: Enable buffers
 109     }
 110
 111     $_TARGETNAME configure -event gdb-attach {
 112         # Without this gdb-attach will first time as probe will fail
 113         reset init
 114     }
 115 }
 116
 117 # Enable the PLL.
 118 # Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
 119 # Note: The PLL output runs at a frequency N times the desired CPU clock.
 120 #       It in unavoidable that the CPU clock drops down to (4 MHz/N) during
 121 #       the initialization!
 122 #       Here: N=4
 123 #       Note that if the PLL is already active at the time this script is
 124 #       called, the effective value of N is the value of CCLKCFG at that time!
 125 #
 126 proc enable_pll {} {
 127     # Disconnect PLL in case it is already connected
 128     if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
 129         # Disconnect it, but leave it enabled
 130         # (This MUST be done in two steps)
 131         mww 0xE01FC080 0x00000001       ;# PLLCON: disconnect PLL
 132         mww 0xE01FC08C 0x000000AA       ;# PLLFEED
 133         mww 0xE01FC08C 0x00000055       ;# PLLFEED
 134     }
 135     # Disable PLL (as it might already be enabled at this time!)
 136     mww 0xE01FC080 0x00000000       ;# PLLCON: disable PLL
 137     mww 0xE01FC08C 0x000000AA       ;# PLLFEED
 138     mww 0xE01FC08C 0x00000055       ;# PLLFEED
 139
 140     # Setup PLL to generate 288 MHz from internal RC oscillator
 141     mww 0xE01FC10C 0x00000000       ;# CLKSRCSEL: IRC
 142     mww 0xE01FC084 0x00000023       ;# PLLCFG: N=1, M=36
 143     mww 0xE01FC08C 0x000000AA       ;# PLLFEED
 144     mww 0xE01FC08C 0x00000055       ;# PLLFEED
 145     mww 0xE01FC080 0x00000001       ;# PLLCON: enable PLL
 146     mww 0xE01FC08C 0x000000AA       ;# PLLFEED
 147     mww 0xE01FC08C 0x00000055       ;# PLLFEED
 148     sleep 100
 149     mww 0xE01FC104 0x00000003       ;# CCLKCFG: divide by 4 (72 MHz)
 150     mww 0xE01FC080 0x00000003       ;# PLLCON: connect PLL
 151     mww 0xE01FC08C 0x000000AA       ;# PLLFEED
 152     mww 0xE01FC08C 0x00000055       ;# PLLFEED
 153 }
 154