tcl/board/icnova_imx53_sodimm.cfg

   1 #################################################################################################
   2 # Author: Benjamin Tietz <benjamin.tietz@in-circuit.de>                                        ;#
   3 # based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com>   ;#
   4 # Kiwigrid GmbH                                                                                ;#
   5 # Generated for In-Circuit i.MX53 SO-Dimm                                                      ;#
   6 #################################################################################################
   7
   8 # The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
   9 source [find target/imx53.cfg]
  10 # Helper for common memory read/modify/write procedures
  11 source [find mem_helper.tcl]
  12
  13 echo "i.MX53 SO-Dimm board lodaded."
  14
  15 # Set reset type
  16 #reset_config srst_only
  17
  18 adapter_khz 3000
  19
  20 $_TARGETNAME configure -event "reset-assert" {
  21         echo "Reseting ...."
  22         #cortex_a dbginit
  23 }
  24
  25 $_TARGETNAME configure -event reset-init { sodimm_init }
  26
  27 global AIPS1_BASE_ADDR
  28 set AIPS1_BASE_ADDR     0x53F00000
  29 global AIPS2_BASE_ADDR
  30 set AIPS2_BASE_ADDR     0x63F00000
  31
  32 proc sodimm_init { } {
  33         echo "Reset-init..."
  34         ; # halt the CPU
  35         halt
  36
  37         echo "HW version [format %x [mrw 0x48]]"
  38
  39         dap apsel 1
  40         DCD
  41
  42         ; # ARM errata ID #468414
  43         set tR [arm mrc 15 0 1 0 1]
  44         arm mcr 15 0 1 0 1 [expr $tR | (1<<5)]  ; # enable L1NEON bit
  45
  46         init_l2cc
  47         init_aips
  48         init_clock
  49
  50         dap apsel 0
  51
  52         ; # Force ARM state
  53         ; #reg cpsr 0x000001D3
  54         arm core_state arm
  55
  56         jtag_rclk 3000
  57 #       adapter_khz 3000
  58 }
  59
  60
  61 # L2CC Cache setup/invalidation/disable
  62 proc init_l2cc { } {
  63         ; #/* explicitly disable L2 cache */
  64         ; #mrc 15, 0, r0, c1, c0, 1
  65         set tR [arm mrc 15 0 1 0 1]
  66         ; #bic r0, r0, #0x2
  67         ; #mcr 15, 0, r0, c1, c0, 1
  68         arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
  69
  70         ; #/* reconfigure L2 cache aux control reg */
  71         ; #mov r0, #0xC0                   /* tag RAM */
  72         ; #add r0, r0, #0x4                /* data RAM */
  73         ; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
  74         ; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
  75         ; #orr r0, r0, #(1 << 22)          /* disable write allocate */
  76
  77         ; #mcr 15, 1, r0, c9, c0, 2
  78         arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
  79 }
  80
  81
  82 # AIPS setup - Only setup MPROTx registers.
  83 # The PACR default values are good.
  84 proc init_aips { } {
  85         ; # Set all MPROTx to be non-bufferable, trusted for R/W,
  86         ; # not forced to user-mode.
  87         global AIPS1_BASE_ADDR
  88         global AIPS2_BASE_ADDR
  89         set VAL                 0x77777777
  90
  91 #       dap apsel 1
  92         mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
  93         mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
  94         mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
  95         mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
  96 #       dap apsel 0
  97 }
  98
  99
 100 proc init_clock { } {
 101         global AIPS1_BASE_ADDR
 102         global AIPS2_BASE_ADDR
 103         set CCM_BASE_ADDR       [expr $AIPS1_BASE_ADDR + 0x000D4000]
 104         set CLKCTL_CCSR         0x0C
 105         set CLKCTL_CBCDR        0x14
 106         set CLKCTL_CBCMR        0x18
 107         set PLL1_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00080000]
 108         set PLL2_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00084000]
 109         set PLL3_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00088000]
 110         set PLL4_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x0008C000]
 111         set CLKCTL_CSCMR1       0x1C
 112         set CLKCTL_CDHIPR       0x48
 113         set PLATFORM_BASE_ADDR  [expr $AIPS2_BASE_ADDR + 0x000A0000]
 114         set CLKCTL_CSCDR1       0x24
 115         set CLKCTL_CCDR         0x04
 116
 117         ; # Switch ARM to step clock
 118         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
 119
 120         return
 121         echo "not returned"
 122         setup_pll $PLL1_BASE_ADDR 800
 123         setup_pll $PLL3_BASE_ADDR 400
 124
 125         ; # Switch peripheral to PLL3
 126         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
 127         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
 128         while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
 129
 130         setup_pll $PLL2_BASE_ADDR 400
 131
 132         ; # Switch peripheral to PLL2
 133         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
 134
 135         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
 136
 137         ; # change uart clk parent to pll2
 138         mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
 139
 140         ; # make sure change is effective
 141         while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
 142
 143         setup_pll $PLL3_BASE_ADDR 216
 144
 145         setup_pll $PLL4_BASE_ADDR 455
 146
 147         ; # Set the platform clock dividers
 148         mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
 149
 150         mww [expr $CCM_BASE_ADDR + 0x10] 0
 151
 152         ; # Switch ARM back to PLL 1.
 153         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
 154
 155         ; # make uart div=6
 156         mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
 157
 158         ; # Restore the default values in the Gate registers
 159         mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
 160         mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
 161         mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
 162         mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
 163         mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
 164         mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
 165         mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
 166         mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
 167
 168         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
 169
 170         ; # for cko - for ARM div by 8
 171         mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
 172 }
 173
 174
 175 proc setup_pll { PLL_ADDR CLK } {
 176         set PLL_DP_CTL          0x00
 177         set PLL_DP_CONFIG       0x04
 178         set PLL_DP_OP           0x08
 179         set PLL_DP_HFS_OP       0x1C
 180         set PLL_DP_MFD          0x0C
 181         set PLL_DP_HFS_MFD      0x20
 182         set PLL_DP_MFN          0x10
 183         set PLL_DP_HFS_MFN      0x24
 184
 185         if {$CLK == 1000} {
 186                 set DP_OP       [expr (10 << 4) + ((1 - 1) << 0)]
 187                 set DP_MFD      [expr (12 - 1)]
 188                 set DP_MFN      5
 189         } elseif {$CLK == 850} {
 190                 set DP_OP       [expr (8 << 4) + ((1 - 1)  << 0)]
 191                 set DP_MFD      [expr (48 - 1)]
 192                 set DP_MFN      41
 193         } elseif {$CLK == 800} {
 194                 set DP_OP       [expr (8 << 4) + ((1 - 1)  << 0)]
 195                 set DP_MFD      [expr (3 - 1)]
 196                 set DP_MFN      1
 197         } elseif {$CLK == 700} {
 198                 set DP_OP       [expr (7 << 4) + ((1 - 1)  << 0)]
 199                 set DP_MFD      [expr (24 - 1)]
 200                 set DP_MFN      7
 201         } elseif {$CLK == 600} {
 202                 set DP_OP       [expr (6 << 4) + ((1 - 1)  << 0)]
 203                 set DP_MFD      [expr (4 - 1)]
 204                 set DP_MFN      1
 205         } elseif {$CLK == 665} {
 206                 set DP_OP       [expr (6 << 4) + ((1 - 1)  << 0)]
 207                 set DP_MFD      [expr (96 - 1)]
 208                 set DP_MFN      89
 209         } elseif {$CLK == 532} {
 210                 set DP_OP       [expr (5 << 4) + ((1 - 1)  << 0)]
 211                 set DP_MFD      [expr (24 - 1)]
 212                 set DP_MFN      13
 213         } elseif {$CLK == 455} {
 214                 set DP_OP       [expr (8 << 4) + ((2 - 1)  << 0)]
 215                 set DP_MFD      [expr (48 - 1)]
 216                 set DP_MFN      71
 217         } elseif {$CLK == 400} {
 218                 set DP_OP       [expr (8 << 4) + ((2 - 1)  << 0)]
 219                 set DP_MFD      [expr (3 - 1)]
 220                 set DP_MFN      1
 221         } elseif {$CLK == 216} {
 222                 set DP_OP       [expr (6 << 4) + ((3 - 1)  << 0)]
 223                 set DP_MFD      [expr (4 - 1)]
 224                 set DP_MFN      3
 225         } else {
 226                 error "Error (setup_dll): clock not found!"
 227         }
 228
 229         mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
 230         mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
 231
 232         mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
 233         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
 234
 235         mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
 236         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
 237
 238         mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
 239         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
 240
 241         mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
 242         while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
 243 }
 244
 245
 246 proc CPU_2_BE_32 { L } {
 247         return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)]
 248 }
 249
 250
 251 # Device Configuration Data
 252 proc DCD { } {
 253 #       dap apsel 1
 254 #*========================================================================================== ======
 255 # Initialization script for 32 bit DDR3 (CS0+CS1)
 256 #*========================================================================================== ======
 257 # Remux D24/D25 to perform Flash-access
 258         mww 0x53fa818C 0x00000000 ; #EIM_RW
 259         mww 0x53fa8180 0x00000000 ; #EIM_CS0
 260         mww 0x53fa8188 0x00000000 ; #EIM_OE
 261         mww 0x53fa817C 0x00000000 ; #A16
 262         mww 0x53fa8178 0x00000000 ; #A17
 263         mww 0x53fa8174 0x00000000 ; #A18
 264         mww 0x53fa8170 0x00000000 ; #A19
 265         mww 0x53fa816C 0x00000000 ; #A20
 266         mww 0x53fa8168 0x00000000 ; #A21
 267         mww 0x53fa819C 0x00000000 ; #DA0
 268         mww 0x53fa81A0 0x00000000 ; #DA1
 269         mww 0x53fa81A4 0x00000000 ; #DA2
 270         mww 0x53fa81A8 0x00000000 ; #DA3
 271         mww 0x53fa81AC 0x00000000 ; #DA4
 272         mww 0x53fa81B0 0x00000000 ; #DA5
 273         mww 0x53fa81B4 0x00000000 ; #DA6
 274         mww 0x53fa81B8 0x00000000 ; #DA7
 275         mww 0x53fa81BC 0x00000000 ; #DA8
 276         mww 0x53fa81C0 0x00000000 ; #DA9
 277         mww 0x53fa81C4 0x00000000 ; #DA10
 278         mww 0x53fa81C8 0x00000000 ; #DA11
 279         mww 0x53fa81CC 0x00000000 ; #DA12
 280         mww 0x53fa81D0 0x00000000 ; #DA13
 281         mww 0x53fa81D4 0x00000000 ; #DA14
 282         mww 0x53fa81D8 0x00000000 ; #DA15
 283         mww 0x53fa8118 0x00000000 ; #D16
 284         mww 0x53fa811C 0x00000000 ; #D17
 285         mww 0x53fa8120 0x00000000 ; #D18
 286         mww 0x53fa8124 0x00000000 ; #D19
 287         mww 0x53fa8128 0x00000000 ; #D20
 288         mww 0x53fa812C 0x00000000 ; #D21
 289         mww 0x53fa8130 0x00000000 ; #D22
 290         mww 0x53fa8134 0x00000000 ; #D23
 291         mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
 292         mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
 293         mww 0x53fa8144 0x00000000 ; #D26
 294         mww 0x53fa8148 0x00000000 ; #D27
 295         mww 0x53fa814C 0x00000000 ; #D28
 296         mww 0x53fa8150 0x00000000 ; #D29
 297         mww 0x53fa8154 0x00000000 ; #D30
 298         mww 0x53fa8158 0x00000000 ; #D31
 299
 300 # DDR3 IOMUX configuration
 301 #* Global pad control options */
 302         mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
 303         mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
 304         mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
 305         mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
 306         mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
 307         mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
 308         mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
 309         mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
 310         mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
 311         mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
 312         mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
 313         mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
 314         mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
 315         mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
 316         mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
 317         mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 318         mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
 319 #       mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
 320         mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
 321         mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
 322         mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
 323         mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
 324         mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
 325         mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
 326         mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
 327 #       mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
 328 #       mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
 329 #       mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
 330 #       mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
 331
 332 #* Data bus byte lane pad drive strength control options */
 333 #       mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
 334 #       mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
 335 #       mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
 336 #       mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
 337 #       mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
 338 #       mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
 339 #       mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
 340 #       mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
 341 #       mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
 342 #       mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
 343 #       mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
 344 #       mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
 345
 346 #* SDCLK pad drive strength control options */
 347 #       mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
 348 #       mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
 349
 350 #* Control and addr bus pad drive strength control options */
 351 #       mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
 352 #       mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
 353 #       mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
 354 #       mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
 355
 356 #       mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
 357 #       mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
 358
 359 # Initialize DDR3 memory - Micron MT41J128M16-187Er
 360 #** Keep for now, same setting as CPU3 board **#
 361         mww 0x63fd901c 0x00008000
 362 #       mww 0x63fd904c 0x01680172 ; #write leveling reg 0
 363 #       mww 0x63fd9050 0x0021017f ; #write leveling reg 1
 364         mww 0x63fd9088 0x32383535 ; #read delay lines
 365         mww 0x63fd9090 0x40383538 ; #write delay lines
 366 #       mww 0x63fd90F8 0x00000800 ; #Measure unit
 367         mww 0x63fd907c 0x0136014d ; #DQS gating 0
 368         mww 0x63fd9080 0x01510141 ; #DQS gating 1
 369 #* CPU3 Board settingr
 370 # Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
 371 #       mww 0x63fd9018 0x00091740 ; #Misc register:
 372 #* Quick Silver board setting
 373 # Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
 374         mww 0x63fd9018 0x00011740 ; #Misc register
 375
 376 # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
 377 #       mww 0x63fd9000 0xc3190000 ; #Main control register
 378 # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
 379         mww 0x63fd9000 0x83190000 ; #Main control register
 380 # tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
 381         mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
 382 # tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
 383         mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
 384 # tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
 385         mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
 386         mww 0x63fd902c 0x000026d2 ; #command delay (default)
 387         mww 0x63fd9030 0x009f0e21 ; #out of reset delays
 388 # Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
 389         mww 0x63fd9008 0x12273030 ; #ODT timings
 390 # tCKE=3; tCKSRX=5; tCKSRE=5
 391         mww 0x63fd9004 0x0002002d
 392 #Power down control
 393 #**********************************
 394 #DDR device configuration:
 395 #**********************************
 396 #**********************************
 397 # CS0:
 398 #**********************************
 399         mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
 400 # Full array self refresh
 401 # Rtt_WR disabled (no ODT at IO CMOS operation)
 402 # Manual self refresh
 403 # CWS=5
 404         mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
 405         mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
 406 # out impedance = RZQ/7
 407 # Rtt_nom disabled (no ODT at IO CMOS operation)
 408 # Aditive latency off
 409 # write leveling disabled
 410 # tdqs (differential?) disabled
 411
 412         mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
 413         mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
 414 #**********************************
 415 # CS1:
 416 #**********************************
 417 #       mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
 418 #       mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
 419 #       mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
 420 #       mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
 421 #       mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
 422 #**********************************
 423
 424
 425         mww 0x63fd9020 0x00001800 ; # Refresh control register
 426         mww 0x63fd9040 0x04b80003 ; # ZQ HW control
 427         mww 0x63fd9058 0x00022227 ; # ODT control register
 428
 429         mww 0x63fd901c 0x00000000
 430
 431 # CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
 432 #       mww 0x53FA8314 = 0
 433 #       mww 0x53FA8320 0x4
 434 #       mww 0x53FD4060 0x01e900f0
 435
 436 #       dap apsel 0
 437 }
 438
 439 # IRAM
 440 $_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
 441
 442 flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME
 443
 444 # vim:filetype=tcl