tcl/board/imx31pdk.cfg

   1 # The IMX31PDK eval board has a single IMX31 chip
   2 source [find target/imx31.cfg]
   3 source [find target/imx.cfg]
   4 $_TARGETNAME configure -event reset-init { imx31pdk_init }
   5
   6 proc self_test {} {
   7         echo "Running 100 iterations of test."
   8         dump_image /ram/test 0x80000000 0x40000
   9         for {set i 0} {$i < 100} {set i [expr $i+1]} {
  10                 echo "Iteration $i"
  11                 reset init
  12                 mww 0x80000000 0x12345678 0x10000
  13                 load_image /ram/test 0x80000000 bin
  14                 verify_image /ram/test 0x80000000 bin
  15         }
  16 }
  17
  18
  19 # Slow fallback frequency
  20 # measure_clk indicates ca. 3-4MHz.
  21 jtag_rclk 1000
  22
  23 proc imx31pdk_init { } {
  24
  25         imx3x_reset
  26
  27         # This setup puts RAM at 0x80000000
  28
  29         mww 0x53FC0000 0x040
  30         mww 0x53F80000 0x074B0B7D
  31
  32         # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
  33         #mww 0x53F80004 0xFF871D50
  34         #mww 0x53F80010 0x00271C1B
  35
  36         # Start 16 bit NorFlash Initialization on CS0
  37         mww 0xb8002000 0x0000CC03
  38         mww 0xb8002004 0xa0330D01
  39         mww 0xb8002008 0x00220800
  40
  41         # Configure CPLD on CS4
  42         mww 0xb8002040 0x0000DCF6
  43         mww 0xb8002044 0x444A4541
  44         mww 0xb8002048 0x44443302
  45
  46         # SDCLK
  47         mww 0x43FAC26C 0
  48
  49         # CAS
  50         mww 0x43FAC270 0
  51
  52         # RAS
  53         mww 0x43FAC274 0
  54
  55         # CS2 (CSD0)
  56         mww 0x43FAC27C 0x1000
  57
  58         # DQM3
  59         mww 0x43FAC284 0
  60
  61         # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
  62         mww 0x43FAC288 0
  63         mww 0x43FAC28C 0
  64         mww 0x43FAC290 0
  65         mww 0x43FAC294 0
  66         mww 0x43FAC298 0
  67         mww 0x43FAC29C 0
  68         mww 0x43FAC2A0 0
  69         mww 0x43FAC2A4 0
  70         mww 0x43FAC2A8 0
  71         mww 0x43FAC2AC 0
  72         mww 0x43FAC2B0 0
  73         mww 0x43FAC2B4 0
  74         mww 0x43FAC2B8 0
  75         mww 0x43FAC2BC 0
  76         mww 0x43FAC2C0 0
  77         mww 0x43FAC2C4 0
  78         mww 0x43FAC2C8 0
  79         mww 0x43FAC2CC 0
  80         mww 0x43FAC2D0 0
  81         mww 0x43FAC2D4 0
  82         mww 0x43FAC2D8 0
  83         mww 0x43FAC2DC 0
  84
  85         # Initialization script for 32 bit DDR on MX31 ADS
  86         mww 0xB8001010 0x00000004
  87         mww 0xB8001004 0x006ac73a
  88         mww 0xB8001000 0x92100000
  89         mww 0x80000f00 0x12344321
  90         mww 0xB8001000 0xa2100000
  91         mww 0x80000000 0x12344321
  92         mww 0x80000000 0x12344321
  93         mww 0xB8001000 0xb2100000
  94         mwb 0x80000033 0xda
  95         mwb 0x81000000 0xff
  96         mww 0xB8001000 0x82226080
  97         mww 0x80000000 0xDEADBEEF
  98         mww 0xB8001010 0x0000000c
  99 }