tcl/board/imx31pdk.cfg

   1 # The IMX31PDK eval board has a single IMX31 chip
   2 source [find target/imx31.cfg]
   3 $_TARGETNAME configure -event reset-init { imx31pdk_init }
   4
   5 proc imx31pdk_init { } {
   6         # This setup puts RAM at 0x80000000
   7
   8         # ========================================
   9         # Init CCM
  10         # ========================================
  11         mww 0x53FC0000 0x040
  12         mww 0x53F80000 0x074B0B7D
  13
  14         sleep 100
  15
  16         # ========================================
  17         # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
  18         # ========================================
  19         mww 0x53F80004 0xFF871D50
  20         mww 0x53F80010 0x00271C1B
  21
  22         # ========================================
  23         # Configure CPLD on CS5
  24         # ========================================
  25         mww 0xb8002050 0x0000DCF6
  26         mww 0xb8002054 0x444A4541
  27         mww 0xb8002058 0x44443302
  28
  29         # ========================================
  30         # SDCLK
  31         # ========================================
  32         mww 0x43FAC26C 0
  33
  34         # ========================================
  35         # CAS
  36         # ========================================
  37         mww 0x43FAC270 0
  38
  39         # ========================================
  40         # RAS
  41         # ========================================
  42         mww 0x43FAC274 0
  43
  44         # ========================================
  45         # CS2 (CSD0)
  46         # ========================================
  47         mww 0x43FAC27C 0x1000
  48
  49         # ========================================
  50         # DQM3
  51         # ========================================
  52         mww 0x43FAC284 0
  53
  54         # ========================================
  55         # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
  56         # ========================================
  57         mww 0x43FAC288 0
  58         mww 0x43FAC28C 0
  59         mww 0x43FAC290 0
  60         mww 0x43FAC294 0
  61         mww 0x43FAC298 0
  62         mww 0x43FAC29C 0
  63         mww 0x43FAC2A0 0
  64         mww 0x43FAC2A4 0
  65         mww 0x43FAC2A8 0
  66         mww 0x43FAC2AC 0
  67         mww 0x43FAC2B0 0
  68         mww 0x43FAC2B4 0
  69         mww 0x43FAC2B8 0
  70         mww 0x43FAC2BC 0
  71         mww 0x43FAC2C0 0
  72         mww 0x43FAC2C4 0
  73         mww 0x43FAC2C8 0
  74         mww 0x43FAC2CC 0
  75         mww 0x43FAC2D0 0
  76         mww 0x43FAC2D4 0
  77         mww 0x43FAC2D8 0
  78         mww 0x43FAC2DC 0
  79
  80         # ========================================
  81         # Initialization script for 32 bit DDR on MX31 PDK
  82         # ========================================
  83         mww 0xB8001010 0x00000004
  84         mww 0xB8001004 0x006ac73a
  85         mww 0xB8001000 0x92100000
  86         mww 0x80000f00 0x12344321
  87         mww 0xB8001000 0xa2100000
  88         mww 0x80000000 0x12344321
  89         mww 0x80000000 0x12344321
  90         mww 0xB8001000 0xb2100000
  91         mwb 0x80000033 0xda
  92         mwb 0x81000000 0xff
  93         mww 0xB8001000 0x82226080
  94         mww 0x80000000 0xDEADBEEF
  95         mww 0xB8001010 0x0000000c
  96 }