tcl/board/imx31pdk.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # The IMX31PDK eval board has a single IMX31 chip
   4 source [find target/imx31.cfg]
   5 source [find target/imx.cfg]
   6 $_TARGETNAME configure -event reset-init { imx31pdk_init }
   7
   8 proc self_test {} {
   9         echo "Running 100 iterations of test."
  10         dump_image /ram/test 0x80000000 0x40000
  11         for {set i 0} {$i < 100} {set i [expr {$i+1}]} {
  12                 echo "Iteration $i"
  13                 reset init
  14                 mww 0x80000000 0x12345678 0x10000
  15                 load_image /ram/test 0x80000000 bin
  16                 verify_image /ram/test 0x80000000 bin
  17         }
  18 }
  19
  20
  21 # Slow fallback frequency
  22 # measure_clk indicates ca. 3-4MHz.
  23 jtag_rclk 1000
  24
  25 proc imx31pdk_init { } {
  26
  27         imx3x_reset
  28
  29         # This setup puts RAM at 0x80000000
  30
  31         mww 0x53FC0000 0x040
  32         mww 0x53F80000 0x074B0B7D
  33
  34         # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
  35         #mww 0x53F80004 0xFF871D50
  36         #mww 0x53F80010 0x00271C1B
  37
  38         # Start 16 bit NorFlash Initialization on CS0
  39         mww 0xb8002000 0x0000CC03
  40         mww 0xb8002004 0xa0330D01
  41         mww 0xb8002008 0x00220800
  42
  43         # Configure CPLD on CS4
  44         mww 0xb8002040 0x0000DCF6
  45         mww 0xb8002044 0x444A4541
  46         mww 0xb8002048 0x44443302
  47
  48         # SDCLK
  49         mww 0x43FAC26C 0
  50
  51         # CAS
  52         mww 0x43FAC270 0
  53
  54         # RAS
  55         mww 0x43FAC274 0
  56
  57         # CS2 (CSD0)
  58         mww 0x43FAC27C 0x1000
  59
  60         # DQM3
  61         mww 0x43FAC284 0
  62
  63         # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
  64         mww 0x43FAC288 0
  65         mww 0x43FAC28C 0
  66         mww 0x43FAC290 0
  67         mww 0x43FAC294 0
  68         mww 0x43FAC298 0
  69         mww 0x43FAC29C 0
  70         mww 0x43FAC2A0 0
  71         mww 0x43FAC2A4 0
  72         mww 0x43FAC2A8 0
  73         mww 0x43FAC2AC 0
  74         mww 0x43FAC2B0 0
  75         mww 0x43FAC2B4 0
  76         mww 0x43FAC2B8 0
  77         mww 0x43FAC2BC 0
  78         mww 0x43FAC2C0 0
  79         mww 0x43FAC2C4 0
  80         mww 0x43FAC2C8 0
  81         mww 0x43FAC2CC 0
  82         mww 0x43FAC2D0 0
  83         mww 0x43FAC2D4 0
  84         mww 0x43FAC2D8 0
  85         mww 0x43FAC2DC 0
  86
  87         # Initialization script for 32 bit DDR on MX31 ADS
  88         mww 0xB8001010 0x00000004
  89         mww 0xB8001004 0x006ac73a
  90         mww 0xB8001000 0x92100000
  91         mww 0x80000f00 0x12344321
  92         mww 0xB8001000 0xa2100000
  93         mww 0x80000000 0x12344321
  94         mww 0x80000000 0x12344321
  95         mww 0xB8001000 0xb2100000
  96         mwb 0x80000033 0xda
  97         mwb 0x81000000 0xff
  98         mww 0xB8001000 0x82226080
  99         mww 0x80000000 0xDEADBEEF
 100         mww 0xB8001010 0x0000000c
 101 }