tcl/board/imx53-m53evk.cfg

   1 #######################################
   2 # DENX M53EVK                         #
   3 # http://www.denx-cs.de/?q=M53EVK     #
   4 # Author: Marek Vasut <marex@denx.de> #
   5 # Based on imx53loco.cfg              #
   6 #######################################
   7
   8 # The DENX M53EVK has on-board JTAG adapter
   9 source [find interface/ftdi/m53evk.cfg]
  10 # The DENX M53EVK board has a single i.MX53 chip
  11 source [find target/imx53.cfg]
  12 # Helper for common memory read/modify/write procedures
  13 source [find mem_helper.tcl]
  14
  15 echo "iMX53 M53EVK board lodaded."
  16
  17 # Set reset type
  18 reset_config trst_and_srst separate trst_open_drain srst_open_drain
  19
  20 # Run at 6 MHz
  21 adapter speed 6000
  22
  23 $_TARGETNAME configure -event "reset-assert" {
  24         echo "Resetting ...."
  25         #cortex_a dbginit
  26 }
  27
  28 $_TARGETNAME configure -event reset-init { m53evk_init }
  29
  30 global AIPS1_BASE_ADDR
  31 set AIPS1_BASE_ADDR     0x53F00000
  32 global AIPS2_BASE_ADDR
  33 set AIPS2_BASE_ADDR     0x63F00000
  34
  35 proc m53evk_init { } {
  36         echo "Reset-init..."
  37         ; # halt the CPU
  38         halt
  39
  40         echo "HW version [format %x [mrw 0x48]]"
  41
  42         dap apsel 1
  43         DCD
  44
  45         ; # ARM errata ID #468414
  46         set tR [arm mrc 15 0 1 0 1]
  47         arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]        ; # enable L1NEON bit
  48
  49         init_l2cc
  50         init_aips
  51         init_clock
  52
  53         dap apsel 0
  54
  55         ; # Force ARM state
  56         ; #reg cpsr 0x000001D3
  57         arm core_state arm
  58 }
  59
  60
  61 # L2CC Cache setup/invalidation/disable
  62 proc init_l2cc { } {
  63         ; #/* explicitly disable L2 cache */
  64         ; #mrc 15, 0, r0, c1, c0, 1
  65         set tR [arm mrc 15 0 1 0 1]
  66         ; #bic r0, r0, #0x2
  67         ; #mcr 15, 0, r0, c1, c0, 1
  68         arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
  69
  70         ; #/* reconfigure L2 cache aux control reg */
  71         ; #mov r0, #0xC0                   /* tag RAM */
  72         ; #add r0, r0, #0x4                /* data RAM */
  73         ; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
  74         ; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
  75         ; #orr r0, r0, #(1 << 22)          /* disable write allocate */
  76
  77         ; #mcr 15, 1, r0, c9, c0, 2
  78         arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
  79 }
  80
  81
  82 # AIPS setup - Only setup MPROTx registers.
  83 # The PACR default values are good.
  84 proc init_aips { } {
  85         ; # Set all MPROTx to be non-bufferable, trusted for R/W,
  86         ; # not forced to user-mode.
  87         global AIPS1_BASE_ADDR
  88         global AIPS2_BASE_ADDR
  89         set VAL                 0x77777777
  90
  91 #       dap apsel 1
  92         mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
  93         mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
  94         mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
  95         mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
  96 #       dap apsel 0
  97 }
  98
  99
 100 proc init_clock { } {
 101         global AIPS1_BASE_ADDR
 102         global AIPS2_BASE_ADDR
 103         set CCM_BASE_ADDR       [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
 104         set CLKCTL_CCSR         0x0C
 105         set CLKCTL_CBCDR        0x14
 106         set CLKCTL_CBCMR        0x18
 107         set PLL1_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x00080000}]
 108         set PLL2_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x00084000}]
 109         set PLL3_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x00088000}]
 110         set PLL4_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
 111         set CLKCTL_CSCMR1       0x1C
 112         set CLKCTL_CDHIPR       0x48
 113         set PLATFORM_BASE_ADDR  [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
 114         set CLKCTL_CSCDR1       0x24
 115         set CLKCTL_CCDR         0x04
 116
 117         ; # Switch ARM to step clock
 118         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
 119
 120         return
 121         echo "not returned"
 122         setup_pll $PLL1_BASE_ADDR 800
 123         setup_pll $PLL3_BASE_ADDR 400
 124
 125         ; # Switch peripheral to PLL3
 126         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
 127         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
 128         while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 129
 130         setup_pll $PLL2_BASE_ADDR 400
 131
 132         ; # Switch peripheral to PLL2
 133         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
 134
 135         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
 136
 137         ; # change uart clk parent to pll2
 138         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
 139
 140         ; # make sure change is effective
 141         while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 142
 143         setup_pll $PLL3_BASE_ADDR 216
 144
 145         setup_pll $PLL4_BASE_ADDR 455
 146
 147         ; # Set the platform clock dividers
 148         mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
 149
 150         mww [expr {$CCM_BASE_ADDR + 0x10}] 0
 151
 152         ; # Switch ARM back to PLL 1.
 153         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
 154
 155         ; # make uart div=6
 156         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
 157
 158         ; # Restore the default values in the Gate registers
 159         mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
 160         mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
 161         mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
 162         mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
 163         mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
 164         mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
 165         mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
 166         mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
 167
 168         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
 169
 170         ; # for cko - for ARM div by 8
 171         mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
 172 }
 173
 174
 175 proc setup_pll { PLL_ADDR CLK } {
 176         set PLL_DP_CTL          0x00
 177         set PLL_DP_CONFIG       0x04
 178         set PLL_DP_OP           0x08
 179         set PLL_DP_HFS_OP       0x1C
 180         set PLL_DP_MFD          0x0C
 181         set PLL_DP_HFS_MFD      0x20
 182         set PLL_DP_MFN          0x10
 183         set PLL_DP_HFS_MFN      0x24
 184
 185         if {$CLK == 1000} {
 186                 set DP_OP       [expr {(10 << 4) + ((1 - 1) << 0)}]
 187                 set DP_MFD      [expr {12 - 1}]
 188                 set DP_MFN      5
 189         } elseif {$CLK == 850} {
 190                 set DP_OP       [expr {(8 << 4) + ((1 - 1)  << 0)}]
 191                 set DP_MFD      [expr {48 - 1}]
 192                 set DP_MFN      41
 193         } elseif {$CLK == 800} {
 194                 set DP_OP       [expr {(8 << 4) + ((1 - 1)  << 0)}]
 195                 set DP_MFD      [expr {3 - 1}]
 196                 set DP_MFN      1
 197         } elseif {$CLK == 700} {
 198                 set DP_OP       [expr {(7 << 4) + ((1 - 1)  << 0)}]
 199                 set DP_MFD      [expr {24 - 1}]
 200                 set DP_MFN      7
 201         } elseif {$CLK == 600} {
 202                 set DP_OP       [expr {(6 << 4) + ((1 - 1)  << 0)}]
 203                 set DP_MFD      [expr {4 - 1}]
 204                 set DP_MFN      1
 205         } elseif {$CLK == 665} {
 206                 set DP_OP       [expr {(6 << 4) + ((1 - 1)  << 0)}]
 207                 set DP_MFD      [expr {96 - 1}]
 208                 set DP_MFN      89
 209         } elseif {$CLK == 532} {
 210                 set DP_OP       [expr {(5 << 4) + ((1 - 1)  << 0)}]
 211                 set DP_MFD      [expr {24 - 1}]
 212                 set DP_MFN      13
 213         } elseif {$CLK == 455} {
 214                 set DP_OP       [expr {(8 << 4) + ((2 - 1)  << 0)}]
 215                 set DP_MFD      [expr {48 - 1}]
 216                 set DP_MFN      71
 217         } elseif {$CLK == 400} {
 218                 set DP_OP       [expr {(8 << 4) + ((2 - 1)  << 0)}]
 219                 set DP_MFD      [expr {3 - 1}]
 220                 set DP_MFN      1
 221         } elseif {$CLK == 216} {
 222                 set DP_OP       [expr {(6 << 4) + ((3 - 1)  << 0)}]
 223                 set DP_MFD      [expr {4 - 1}]
 224                 set DP_MFN      3
 225         } else {
 226                 error "Error (setup_dll): clock not found!"
 227         }
 228
 229         mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
 230         mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
 231
 232         mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
 233         mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
 234
 235         mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
 236         mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
 237
 238         mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
 239         mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
 240
 241         mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
 242         while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
 243 }
 244
 245
 246 proc CPU_2_BE_32 { L } {
 247         return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
 248 }
 249
 250
 251 # Device Configuration Data
 252 proc DCD { } {
 253 #       dap apsel 1
 254         mww 0x53fa86f4 0x00000000        ;# GRP_DDRMODE_CTL
 255         mww 0x53fa8714 0x00000000        ;# GRP_DDRMODE
 256         mww 0x53fa86fc 0x00000000        ;# GRP_DDRPKE
 257         mww 0x53fa8724 0x04000000        ;# GRP_DDR_TYPE
 258
 259         mww 0x53fa872c 0x00300000        ;# GRP_B3DS
 260         mww 0x53fa8554 0x00300000        ;# DRAM_DQM3
 261         mww 0x53fa8558 0x00300040        ;# DRAM_SDQS3
 262
 263         mww 0x53fa8728 0x00300000        ;# GRP_B2DS
 264         mww 0x53fa8560 0x00300000        ;# DRAM_DQM2
 265         mww 0x53fa8568 0x00300040        ;# DRAM_SDQS2
 266
 267         mww 0x53fa871c 0x00300000        ;# GRP_B1DS
 268         mww 0x53fa8594 0x00300000        ;# DRAM_DQM1
 269         mww 0x53fa8590 0x00300040        ;# DRAM_SDQS1
 270
 271         mww 0x53fa8718 0x00300000        ;# GRP_B0DS
 272         mww 0x53fa8584 0x00300000        ;# DRAM_DQM0
 273         mww 0x53fa857c 0x00300040        ;# DRAM_SDQS0
 274
 275         mww 0x53fa8578 0x00300000        ;# DRAM_SDCLK_0
 276         mww 0x53fa8570 0x00300000        ;# DRAM_SDCLK_1
 277
 278         mww 0x53fa8574 0x00300000        ;# DRAM_CAS
 279         mww 0x53fa8588 0x00300000        ;# DRAM_RAS
 280         mww 0x53fa86f0 0x00300000        ;# GRP_ADDDS
 281         mww 0x53fa8720 0x00300000        ;# GRP_CTLDS
 282
 283         mww 0x53fa8564 0x00300040        ;# DRAM_SDODT1
 284         mww 0x53fa8580 0x00300040        ;# DRAM_SDODT0
 285
 286         # Initialize DDR2 memory
 287         mww 0x63fd9088 0x32383535
 288         mww 0x63fd9090 0x40383538
 289         mww 0x63fd907c 0x0136014d
 290         mww 0x63fd9080 0x01510141
 291
 292         mww 0x63fd9018 0x00011740
 293         mww 0x63fd9000 0xc3190000
 294         mww 0x63fd900c 0x555952e3
 295         mww 0x63fd9010 0xb68e8b63
 296         mww 0x63fd9014 0x01ff00db
 297         mww 0x63fd902c 0x000026d2
 298         mww 0x63fd9030 0x009f0e21
 299         mww 0x63fd9008 0x12273030
 300         mww 0x63fd9004 0x0002002d
 301         mww 0x63fd901c 0x00008032
 302         mww 0x63fd901c 0x00008033
 303         mww 0x63fd901c 0x00028031
 304         mww 0x63fd901c 0x092080b0
 305         mww 0x63fd901c 0x04008040
 306         mww 0x63fd901c 0x0000803a
 307         mww 0x63fd901c 0x0000803b
 308         mww 0x63fd901c 0x00028039
 309         mww 0x63fd901c 0x09208138
 310         mww 0x63fd901c 0x04008048
 311         mww 0x63fd9020 0x00001800
 312         mww 0x63fd9040 0x04b80003
 313         mww 0x63fd9058 0x00022227
 314         mww 0x63fd901c 0x00000000
 315 #       dap apsel 0
 316 }
 317
 318 # vim:filetype=tcl