tcl/board/imx53loco.cfg

   1 ##################################################################################
   2 # Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> #
   3 # Kiwigrid GmbH                                                                  #
   4 ##################################################################################
   5
   6 # The IMX53LOCO (QSB) board has a single IMX53 chip
   7 source [find target/imx53.cfg]
   8 # Helper for common memory read/modify/write procedures
   9 source [find mem_helper.tcl]
  10
  11 echo "iMX53 Loco board lodaded."
  12
  13 # Set reset type
  14 #reset_config srst_only
  15
  16 adapter_khz 3000
  17
  18 #jtag_nsrst_delay 200
  19 #jtag_ntrst_delay 200
  20
  21 $_TARGETNAME configure -event "reset-assert" {
  22         echo "Reseting ...."
  23         #cortex_a8 dbginit
  24 }
  25
  26 $_TARGETNAME configure -event reset-init { loco_init }
  27
  28 global AIPS1_BASE_ADDR
  29 set AIPS1_BASE_ADDR     0x53F00000
  30 global AIPS2_BASE_ADDR
  31 set AIPS2_BASE_ADDR     0x63F00000
  32
  33 proc loco_init { } {
  34         echo "Reset-init..."
  35         ; # halt the CPU
  36         halt
  37
  38         echo "HW version [format %x [mrw 0x48]]"
  39
  40         dap apsel 1
  41         DCD
  42
  43         ; # ARM errata ID #468414
  44         set tR [arm mrc 15 0 1 0 1]
  45         arm mcr 15 0 1 0 1 [expr $tR | (1<<5)]  ; # enable L1NEON bit
  46
  47         init_l2cc
  48         init_aips
  49         init_clock
  50
  51         dap apsel 0
  52
  53         ; # Force ARM state
  54         ; #reg cpsr 0x000001D3
  55         arm core_state arm
  56
  57         jtag_rclk 3000
  58 #       adapter_khz 3000
  59 }
  60
  61
  62 # L2CC Cache setup/invalidation/disable
  63 proc init_l2cc { } {
  64         ; #/* explicitly disable L2 cache */
  65         ; #mrc 15, 0, r0, c1, c0, 1
  66         set tR [arm mrc 15 0 1 0 1]
  67         ; #bic r0, r0, #0x2
  68         ; #mcr 15, 0, r0, c1, c0, 1
  69         arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
  70
  71         ; #/* reconfigure L2 cache aux control reg */
  72         ; #mov r0, #0xC0                   /* tag RAM */
  73         ; #add r0, r0, #0x4                /* data RAM */
  74         ; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
  75         ; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
  76         ; #orr r0, r0, #(1 << 22)          /* disable write allocate */
  77
  78         ; #mcr 15, 1, r0, c9, c0, 2
  79         arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
  80 }
  81
  82
  83 # AIPS setup - Only setup MPROTx registers.
  84 # The PACR default values are good.
  85 proc init_aips { } {
  86         ; # Set all MPROTx to be non-bufferable, trusted for R/W,
  87         ; # not forced to user-mode.
  88         global AIPS1_BASE_ADDR
  89         global AIPS2_BASE_ADDR
  90         set VAL                 0x77777777
  91
  92 #       dap apsel 1
  93         mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
  94         mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
  95         mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
  96         mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
  97 #       dap apsel 0
  98 }
  99
 100
 101 proc init_clock { } {
 102         global AIPS1_BASE_ADDR
 103         global AIPS2_BASE_ADDR
 104         set CCM_BASE_ADDR       [expr $AIPS1_BASE_ADDR + 0x000D4000]
 105         set CLKCTL_CCSR         0x0C
 106         set CLKCTL_CBCDR        0x14
 107         set CLKCTL_CBCMR        0x18
 108         set PLL1_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00080000]
 109         set PLL2_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00084000]
 110         set PLL3_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x00088000]
 111         set PLL4_BASE_ADDR      [expr $AIPS2_BASE_ADDR + 0x0008C000]
 112         set CLKCTL_CSCMR1       0x1C
 113         set CLKCTL_CDHIPR       0x48
 114         set PLATFORM_BASE_ADDR  [expr $AIPS2_BASE_ADDR + 0x000A0000]
 115         set CLKCTL_CSCDR1       0x24
 116         set CLKCTL_CCDR         0x04
 117
 118         ; # Switch ARM to step clock
 119         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
 120
 121         return
 122         echo "not returned"
 123         setup_pll $PLL1_BASE_ADDR 800
 124         setup_pll $PLL3_BASE_ADDR 400
 125
 126         ; # Switch peripheral to PLL3
 127         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
 128         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
 129         while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
 130
 131         setup_pll $PLL2_BASE_ADDR 400
 132
 133         ; # Switch peripheral to PLL2
 134         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
 135
 136         mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
 137
 138         ; # change uart clk parent to pll2
 139         mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
 140
 141         ; # make sure change is effective
 142         while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
 143
 144         setup_pll $PLL3_BASE_ADDR 216
 145
 146         setup_pll $PLL4_BASE_ADDR 455
 147
 148         ; # Set the platform clock dividers
 149         mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
 150
 151         mww [expr $CCM_BASE_ADDR + 0x10] 0
 152
 153         ; # Switch ARM back to PLL 1.
 154         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
 155
 156         ; # make uart div=6
 157         mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
 158
 159         ; # Restore the default values in the Gate registers
 160         mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
 161         mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
 162         mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
 163         mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
 164         mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
 165         mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
 166         mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
 167         mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
 168
 169         mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
 170
 171         ; # for cko - for ARM div by 8
 172         mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
 173 }
 174
 175
 176 proc setup_pll { PLL_ADDR CLK } {
 177         set PLL_DP_CTL          0x00
 178         set PLL_DP_CONFIG       0x04
 179         set PLL_DP_OP           0x08
 180         set PLL_DP_HFS_OP       0x1C
 181         set PLL_DP_MFD          0x0C
 182         set PLL_DP_HFS_MFD      0x20
 183         set PLL_DP_MFN          0x10
 184         set PLL_DP_HFS_MFN      0x24
 185
 186         if {$CLK == 1000} {
 187                 set DP_OP       [expr (10 << 4) + ((1 - 1) << 0)]
 188                 set DP_MFD      [expr (12 - 1)]
 189                 set DP_MFN      5
 190         } elseif {$CLK == 850} {
 191                 set DP_OP       [expr (8 << 4) + ((1 - 1)  << 0)]
 192                 set DP_MFD      [expr (48 - 1)]
 193                 set DP_MFN      41
 194         } elseif {$CLK == 800} {
 195                 set DP_OP       [expr (8 << 4) + ((1 - 1)  << 0)]
 196                 set DP_MFD      [expr (3 - 1)]
 197                 set DP_MFN      1
 198         } elseif {$CLK == 700} {
 199                 set DP_OP       [expr (7 << 4) + ((1 - 1)  << 0)]
 200                 set DP_MFD      [expr (24 - 1)]
 201                 set DP_MFN      7
 202         } elseif {$CLK == 600} {
 203                 set DP_OP       [expr (6 << 4) + ((1 - 1)  << 0)]
 204                 set DP_MFD      [expr (4 - 1)]
 205                 set DP_MFN      1
 206         } elseif {$CLK == 665} {
 207                 set DP_OP       [expr (6 << 4) + ((1 - 1)  << 0)]
 208                 set DP_MFD      [expr (96 - 1)]
 209                 set DP_MFN      89
 210         } elseif {$CLK == 532} {
 211                 set DP_OP       [expr (5 << 4) + ((1 - 1)  << 0)]
 212                 set DP_MFD      [expr (24 - 1)]
 213                 set DP_MFN      13
 214         } elseif {$CLK == 455} {
 215                 set DP_OP       [expr (8 << 4) + ((2 - 1)  << 0)]
 216                 set DP_MFD      [expr (48 - 1)]
 217                 set DP_MFN      71
 218         } elseif {$CLK == 400} {
 219                 set DP_OP       [expr (8 << 4) + ((2 - 1)  << 0)]
 220                 set DP_MFD      [expr (3 - 1)]
 221                 set DP_MFN      1
 222         } elseif {$CLK == 216} {
 223                 set DP_OP       [expr (6 << 4) + ((3 - 1)  << 0)]
 224                 set DP_MFD      [expr (4 - 1)]
 225                 set DP_MFN      3
 226         } else {
 227                 error "Error (setup_dll): clock not found!"
 228         }
 229
 230         mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
 231         mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
 232
 233         mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
 234         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
 235
 236         mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
 237         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
 238
 239         mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
 240         mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
 241
 242         mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
 243         while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
 244 }
 245
 246
 247 proc CPU_2_BE_32 { L } {
 248         return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)]
 249 }
 250
 251
 252 # Device Configuration Data
 253 proc DCD { } {
 254 #       dap apsel 1
 255         mww 0x53FA8554 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
 256         mww 0x53FA8558 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
 257         mww 0x53FA8560 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
 258         mww 0x53FA8564 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT
 259         mww 0x53FA8568 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
 260         mww 0x53FA8570 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
 261         mww 0x53FA8574 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
 262         mww 0x53FA8578 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
 263         mww 0x53FA857c 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
 264         mww 0x53FA8580 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
 265         mww 0x53FA8584 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
 266         mww 0x53FA8588 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
 267         mww 0x53FA8590 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
 268         mww 0x53FA8594 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
 269         mww 0x53FA86f0 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_ADDDS
 270         mww 0x53FA86f4 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 271         mww 0x53FA86fc 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
 272         mww 0x53FA8714 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode
 273         mww 0x53FA8718 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B0DS
 274         mww 0x53FA871c 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B1DS
 275         mww 0x53FA8720 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_CTLDS
 276         mww 0x53FA8724 0x04000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=
 277         mww 0x53FA8728 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B2DS
 278         mww 0x53FA872c 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B3DS
 279
 280         # Initialize DDR2 memory
 281         mww 0x63FD9088 0x35343535       ;# ESDCTL_RDDLCTL
 282         mww 0x63FD9090 0x4d444c44       ;# ESDCTL_WRDLCTL
 283         mww 0x63FD907c 0x01370138       ;# ESDCTL_DGCTRL0
 284         mww 0x63FD9080 0x013b013c       ;# ESDCTL_DGCTRL1
 285         mww 0x63FD9018 0x00011740       ;# ESDCTL_ESDMISC
 286         mww 0x63FD9000 0xc3190000       ;# ESDCTL_ESDCTL
 287         mww 0x63FD900c 0x9f5152e3       ;# ESDCTL_ESDCFG0
 288         mww 0x63FD9010 0xb68e8a63       ;# ESDCTL_ESDCFG1
 289         mww 0x63FD9014 0x01ff00db       ;# ESDCTL_ESDCFG2
 290         mww 0x63FD902c 0x000026d2       ;# ESDCTL_ESDRWD
 291         mww 0x63FD9030 0x009f0e21       ;# ESDCTL_ESDOR
 292         mww 0x63FD9008 0x12273030       ;# ESDCTL_ESDOTC
 293         mww 0x63FD9004 0x0002002d       ;# ESDCTL_ESDPDC
 294         mww 0x63FD901c 0x00008032       ;# ESDCTL_ESDSCR
 295         mww 0x63FD901c 0x00008033       ;# ESDCTL_ESDSCR
 296         mww 0x63FD901c 0x00028031       ;# ESDCTL_ESDSCR
 297         mww 0x63FD901c 0x052080b0       ;# ESDCTL_ESDSCR
 298         mww 0x63FD901c 0x04008040       ;# ESDCTL_ESDSCR
 299         mww 0x63FD901c 0x0000803a       ;# ESDCTL_ESDSCR
 300         mww 0x63FD901c 0x0000803b       ;# ESDCTL_ESDSCR
 301         mww 0x63FD901c 0x00028039       ;# ESDCTL_ESDSCR
 302         mww 0x63FD901c 0x05208138       ;# ESDCTL_ESDSCR
 303         mww 0x63FD901c 0x04008048       ;# ESDCTL_ESDSCR
 304         mww 0x63FD9020 0x00005800       ;# ESDCTL_ESDREF
 305         mww 0x63FD9040 0x04b80003       ;# ESDCTL_ZQHWCTRL
 306         mww 0x63FD9058 0x00022227       ;# ESDCTL_ODTCTRL
 307         mww 0x63FD901C 0x00000000       ;# ESDCTL_ESDSCR
 308 #       dap apsel 0
 309 }
 310
 311 # vim:filetype=tcl