tcl/board/lubbock.cfg

   1 # Intel "Lubbock" Development Board with PXA255 (dbpxa255)
   2 #  Obsolete; this was Intel's original PXA255 development system
   3 #  Board also had CPU cards for SA1100, PXA210, PXA250, and more.
   4
   5 source [find target/pxa255.cfg]
   6
   7 jtag_nsrst_delay 250
   8 jtag_ntrst_delay 250
   9
  10 # NOTE: until after pinmux and such are set up, only CS0 is
  11 # available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.
  12
  13 # CS0, CS1 -- two banks of CFI flash, 32 MBytes each
  14 # each bank is 32-bits wide, two 16-bit chips in parallel
  15 flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  16 flash bank cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
  17
  18 # CS2 low -- FPGA registers
  19 # CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
  20 $_TARGETNAME configure -work-area-phys 0x0a0f0000
  21
  22 $_TARGETNAME configure -event reset-assert-pre \
  23         "$_TARGETNAME configure -work-area-size 0"
  24
  25 # Make the hex led display a number, assuming CS2 is set up
  26 # and all digits have been enabled through the FPGA.
  27 proc hexled {u32} {
  28         mww 0x08000010 $u32
  29 }
  30
  31 # CS3 -- Ethernet
  32 # CS4 -- SA1111
  33 # CS5 -- PCMCIA
  34
  35 # NOTE:  system console normally uses the FF UART connector
  36
  37 proc lubbock_init {target} {
  38
  39         puts "Initialize PXA255 Lubbock board"
  40
  41         # (1) pinmux
  42
  43         # GPSR0..GPSR2
  44         mww 0x40e00018 0x00008000
  45         mww 0x40e0001c 0x00FC0382
  46         mww 0x40e00020 0x0001FFFF
  47         # GPDR0..GPDR2
  48         mww 0x40e0000c 0x0060A800
  49         mww 0x40e00010 0x00FF0382
  50         mww 0x40e00014 0x0001C000
  51         # GAFR0_[LU]..GAFR2_[LU]
  52         mww 0x40e00054 0x98400000
  53         mww 0x40e00058 0x00002950
  54         mww 0x40e0005c 0x000A9558
  55         mww 0x40e00060 0x0005AAAA
  56         mww 0x40e00064 0xA0000000
  57         mww 0x40e00068 0x00000002
  58
  59         # write PSSR, enable GPIOs
  60         mww 0x40f00000 0x00000020
  61
  62         # write LED ctrl register ... ones disable
  63         # high byte, 8 hex leds; low byte, 8 discretes
  64         mwh 0x08000040 0xf0ff
  65
  66         hexled 0x0000
  67
  68         # (2) Address space setup
  69
  70         # MSC0/MSC1/MSC2
  71         mww 0x48000008 0x23f223f2
  72         mww 0x4800000c 0x3ff1a441
  73         mww 0x48000010 0x7ff97ff1
  74         # pcmcia/cf
  75         mww 0x48000014 0x00000000
  76         mww 0x48000028 0x00010504
  77         mww 0x4800002c 0x00010504
  78         mww 0x48000030 0x00010504
  79         mww 0x48000034 0x00010504
  80         mww 0x48000038 0x00004715
  81         mww 0x4800003c 0x00004715
  82
  83         hexled 0x1111
  84
  85         # (3) SDRAM setup
  86         # REVISIT this looks dubious ... no refresh cycles
  87         mww 0x48000004 0x03CA4018
  88         mww 0x48000004 0x004B4018
  89         mww 0x48000004 0x000B4018
  90         mww 0x48000004 0x000BC018
  91         mww 0x48000000 0x00001AC8
  92         mww 0x48000000 0x00001AC9
  93
  94         mww 0x48000040 0x00000000
  95
  96         # FIXME -- setup:
  97         #  CLOCKS (and faster JTAG)
  98         #  enable icache
  99
 100         # FIXME SRAM isn't working
 101         # $target configure -work-area-size 0x10000
 102
 103         hexled 0x2222
 104
 105         flash probe 0
 106         flash probe 1
 107
 108         hexled 0xcafe
 109 }
 110 $_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME"