tcl/board/nxp_imx7sabre.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # NXP IMX7SABRE board
   4 # use on-board JTAG header
   5 transport select jtag
   6
   7 # set a safe speed, can be overridden
   8 adapter speed 1000
   9
  10 # reset configuration has TRST and SRST support
  11 reset_config trst_and_srst srst_push_pull
  12 # need at least 100ms delay after SRST release for JTAG
  13 adapter srst delay 100
  14
  15 # source the target file
  16 source [find target/imx7.cfg]
  17 # import mrw proc
  18 source [find mem_helper.tcl]
  19
  20 # function to disable the on-chip watchdog
  21 proc imx7_disable_wdog { } {
  22         # echo "disable watchdog power-down counter"
  23         mwh phys 0x30280008 0x00
  24 }
  25
  26 proc imx7_uart_dbgconf { } {
  27         # disable response to debug_req signal for uart1
  28         mww phys 0x308600b4 0x0a60
  29 }
  30
  31 proc check_bits_set_32 { addr mask } {
  32     while { [expr {[mrw $addr] & $mask} == 0] } { }
  33 }
  34
  35 proc apply_dcd { } {
  36     # echo "apply dcd"
  37
  38     mww phys 0x30340004 0x4F400005
  39     # Clear then set bit30 to ensure exit from DDR retention
  40     mww phys 0x30360388 0x40000000
  41     mww phys 0x30360384 0x40000000
  42
  43     mww phys 0x30391000 0x00000002
  44     mww phys 0x307a0000 0x01040001
  45     mww phys 0x307a01a0 0x80400003
  46     mww phys 0x307a01a4 0x00100020
  47     mww phys 0x307a01a8 0x80100004
  48     mww phys 0x307a0064 0x00400046
  49     mww phys 0x307a0490 0x00000001
  50     mww phys 0x307a00d0 0x00020083
  51     mww phys 0x307a00d4 0x00690000
  52     mww phys 0x307a00dc 0x09300004
  53     mww phys 0x307a00e0 0x04080000
  54     mww phys 0x307a00e4 0x00100004
  55     mww phys 0x307a00f4 0x0000033f
  56     mww phys 0x307a0100 0x09081109
  57     mww phys 0x307a0104 0x0007020d
  58     mww phys 0x307a0108 0x03040407
  59     mww phys 0x307a010c 0x00002006
  60     mww phys 0x307a0110 0x04020205
  61     mww phys 0x307a0114 0x03030202
  62     mww phys 0x307a0120 0x00000803
  63     mww phys 0x307a0180 0x00800020
  64     mww phys 0x307a0184 0x02000100
  65     mww phys 0x307a0190 0x02098204
  66     mww phys 0x307a0194 0x00030303
  67     mww phys 0x307a0200 0x00000016
  68     mww phys 0x307a0204 0x00171717
  69     mww phys 0x307a0214 0x04040404
  70     mww phys 0x307a0218 0x0f040404
  71     mww phys 0x307a0240 0x06000604
  72     mww phys 0x307a0244 0x00000001
  73     mww phys 0x30391000 0x00000000
  74     mww phys 0x30790000 0x17420f40
  75     mww phys 0x30790004 0x10210100
  76     mww phys 0x30790010 0x00060807
  77     mww phys 0x307900b0 0x1010007e
  78     mww phys 0x3079009c 0x00000d6e
  79     mww phys 0x30790020 0x08080808
  80     mww phys 0x30790030 0x08080808
  81     mww phys 0x30790050 0x01000010
  82     mww phys 0x30790050 0x00000010
  83
  84     mww phys 0x307900c0 0x0e407304
  85     mww phys 0x307900c0 0x0e447304
  86     mww phys 0x307900c0 0x0e447306
  87
  88     check_bits_set_32 0x307900c4 0x1
  89
  90     mww phys 0x307900c0 0x0e447304
  91     mww phys 0x307900c0 0x0e407304
  92
  93
  94     mww phys 0x30384130 0x00000000
  95     mww phys 0x30340020 0x00000178
  96     mww phys 0x30384130 0x00000002
  97     mww phys 0x30790018 0x0000000f
  98
  99     check_bits_set_32 0x307a0004 0x1
 100 }
 101
 102 # disable internal reset-assert handling to
 103 # allow reset-init to work
 104 $_TARGETNAME.0 configure -event reset-assert ""
 105 $_TARGETNAME.1 configure -event reset-assert ""
 106 $_TARGETNAME_2 configure -event reset-assert ""
 107
 108 $_TARGETNAME.0 configure -event reset-init {
 109     global _CHIPNAME
 110     imx7_disable_wdog
 111     imx7_uart_dbgconf
 112     apply_dcd
 113     $_CHIPNAME.dap memaccess 0
 114 }
 115
 116 target smp $_TARGETNAME.0 $_TARGETNAME.1