tcl/board/olimex_sam9_l9260.cfg

   1 ################################################################################
   2 # Olimex SAM9-L9260 Development Board
   3 #
   4 # http://www.olimex.com/dev/sam9-L9260.html
   5 #
   6 # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
   7 #                     PMC configured for external 18.432 MHz crystal
   8 #
   9 # 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
  10 # 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
  11 # Dataflash : 1 x Atmel AT45DB161D, 16Mbit
  12 #
  13 ################################################################################
  14
  15 source [find target/at91sam9260.cfg]
  16
  17 # NTRST_E jumper is enabled by default, so we don't need to override the reset
  18 # config.
  19 #reset_config srst_only
  20
  21 $_TARGETNAME configure -event reset-start {
  22         # At reset, CPU runs at 32.768 kHz.  JTAG frequency must be 6 times slower if
  23         # RCLK is not supported.
  24         jtag_rclk 5
  25         halt
  26
  27         # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may
  28         # be enabled... use physical address.
  29         mww phys 0xfffffd08 0xa5000501
  30 }
  31
  32 $_TARGETNAME configure -event reset-init {
  33         mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
  34
  35         ##
  36         # Clock configuration for 99.328 MHz main clock.
  37         ##
  38     echo "Setting up clock"
  39         mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup
  40         sleep 20                  # wait 20 ms (need 15.6 ms for startup)
  41         mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz)
  42         sleep 10                  # wait 10 ms
  43         mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
  44         sleep 20                  # wait 20 ms (need 1.9 ms for startup)
  45         mww 0xfffffc30 0x00000101 # PMC_MCKR : no scale on proc clock, master is proc / 2
  46         sleep 10                  # wait 10 ms
  47         mww 0xfffffc30 0x00000102 # PMC_MCKR : switch to PLLA (99.328 MHz)
  48
  49         # Increase JTAG speed to 6 MHz if RCLK is not supported.
  50         jtag_rclk 6000
  51
  52         arm7_9 dcc_downloads enable # Enable faster DCC downloads.
  53
  54         ##
  55         # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
  56         ##
  57     echo "Configuring SDRAM"
  58         mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31
  59         mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31
  60
  61         mww 0xffffef1c 0x00010002 # EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
  62
  63         mww 0xffffea08 0x85237259 # SDRAMC_CR : configure SDRAM for Samsung chips
  64
  65         mww 0xffffea00 0x1        # SDRAMC_MR : issue NOP command
  66         mww 0x20000000 0
  67         mww 0xffffea00 0x2        # SDRAMC_MR : issue an 'All Banks Precharge' command
  68         mww 0x20000000 0
  69         mww 0xffffea00 0x4        # SDRAMC_MR : issue 8 x 'Auto-Refresh' command
  70         mww 0x20000000 0
  71         mww 0xffffea00 0x4
  72         mww 0x20000000 0
  73         mww 0xffffea00 0x4
  74         mww 0x20000000 0
  75         mww 0xffffea00 0x4
  76         mww 0x20000000 0
  77         mww 0xffffea00 0x4
  78         mww 0x20000000 0
  79         mww 0xffffea00 0x4
  80         mww 0x20000000 0
  81         mww 0xffffea00 0x4
  82         mww 0x20000000 0
  83         mww 0xffffea00 0x4
  84         mww 0x20000000 0
  85         mww 0xffffea00 0x3        # SDRAMC_MR : issue a 'Load Mode Register' command
  86         mww 0x20000000 0
  87         mww 0xffffea00 0x0        # SDRAMC_MR : normal mode
  88         mww 0x20000000 0
  89
  90         mww 0xffffea04 0x2b6      # SDRAMC_TR : set refresh timer count to 7 us
  91
  92     ##
  93     # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
  94     ##
  95     echo "Configuring NAND flash"
  96     mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
  97     mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
  98     mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
  99     mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
 100     mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
 101     mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
 102
 103     mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
 104
 105     mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
 106     mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
 107     mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
 108     mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
 109                                #             3 TDF cycles, no optimization
 110
 111     mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
 112     mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
 113
 114     nand probe at91sam9260.flash
 115
 116     ##
 117     # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
 118     ##
 119     echo "Setting up dataflash"
 120     mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
 121                                #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
 122     mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
 123     mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
 124     mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
 125
 126     mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
 127     mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
 128     mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
 129
 130     mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
 131                                #             250ns delay before SPCK, 250ns b/n tx
 132
 133     mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
 134     mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
 135 }
 136
 137 nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
 138 at91sam9 cle 0 22
 139 at91sam9 ale 0 21
 140 at91sam9 rdy_busy 0 0xfffff800 13
 141 at91sam9 ce 0 0xfffff800 14