tcl/board/or1k_generic.cfg

   1 # If you want to use the VJTAG TAP or the XILINX BSCAN,
   2 # you must set your FPGA TAP ID here
   3
   4 set FPGATAPID 0x020b30dd
   5
   6 # Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
   7 if { [info exists TAP_TYPE] == 0} {
   8    set TAP_TYPE VJTAG
   9 }
  10
  11 # Set your chip name
  12 set CHIPNAME or1200
  13
  14 source [find target/or1k.cfg]
  15
  16 # Set the servers polling period to 1ms (needed to JSP Server)
  17 poll_period 1
  18
  19 # Set the adapter speed
  20 adapter_khz 3000
  21
  22 # Enable the target description feature
  23 gdb_target_description enable
  24
  25 # Add a new register in the cpu register list. This register will be
  26 # included in the generated target descriptor file.
  27 # format is addreg [name] [address] [feature] [reg_group]
  28 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
  29
  30 # Override default init_reset
  31 proc init_reset {mode} {
  32         soft_reset_halt
  33         resume
  34 }
  35
  36 # Target initialization
  37 init
  38 echo "Halting processor"
  39 halt
  40
  41 foreach name [target names] {
  42         set y [$name cget -endian]
  43         set z [$name cget -type]
  44         puts [format "Chip is %s, Endian: %s, type: %s" \
  45               $name $y $z]
  46 }
  47
  48 set c_blue  "\033\[01;34m"
  49 set c_reset "\033\[0m"
  50
  51 puts [format "%sTarget ready...%s" $c_blue $c_reset]