tcl/board/phytec_lpc3250.cfg

   1 source [find target/lpc3250.cfg]
   2
   3 adapter_nsrst_delay 200
   4 jtag_ntrst_delay 1
   5 adapter_khz 200
   6 reset_config trst_and_srst separate
   7
   8 arm7_9 dcc_downloads enable
   9
  10 $_TARGETNAME configure -event gdb-attach { reset init }
  11
  12 $_TARGETNAME configure -event reset-start {
  13              arm7_9 fast_memory_access disable
  14              adapter_khz 200
  15 }
  16
  17 $_TARGETNAME configure -event reset-end {
  18              adapter_khz 6000
  19              arm7_9 fast_memory_access enable
  20 }
  21
  22 $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
  23
  24 # Bare-bones initialization of core clocks and SDRAM
  25 proc phytec_lpc3250_init { } {
  26         # Set clock dividers
  27         #   ARMCLK = 266.5 MHz
  28         #   HCLK   = 133.25 MHz
  29         #   PERIPHCLK = 13.325 MHz
  30         mww 0x400040BC 0
  31         mww 0x40004050 0x140
  32         mww 0x40004040 0x4D
  33         mww 0x40004058 0x16250
  34
  35         # Init PLLs
  36         mww 0x40004044 0x006
  37         sleep 1 busy
  38         mww 0x40004044 0x106
  39         sleep 1 busy
  40         mww 0x40004044 0x006
  41         sleep 1 busy
  42         mww 0x40004048 0x2
  43
  44         # Init SDRAM with 133 MHz timings
  45         mww 0x40028134 0x00FFFFFF
  46         mww 0x4002802C 0x00000008
  47
  48         mww 0x31080000 1
  49         mww 0x31080008 0
  50         mww 0x40004068 0x1C000
  51         mww 0x31080028 0x11
  52
  53         mww 0x31080400 0
  54         mww 0x31080440 0
  55         mww 0x31080460 0
  56         mww 0x31080480 0
  57
  58         # Delays
  59         mww 0x31080030 1
  60         mww 0x31080034 6
  61         mww 0x31080038 10
  62         mww 0x31080044 1
  63         mww 0x31080048 9
  64         mww 0x3108004C 12
  65         mww 0x31080050 10
  66         mww 0x31080054 1
  67         mww 0x31080058 1
  68         mww 0x3108005C 0
  69
  70         mww 0x31080100 0x5680
  71         mww 0x31080104 0x302
  72
  73         # Init sequence
  74         mww 0x31080020 0x193
  75         sleep 1 busy
  76         mww 0x31080024 1
  77         mww 0x31080020 0x113
  78         sleep 1 busy
  79         mww 0x31080020 0x013
  80         sleep 1 busy
  81         mww 0x31080024 65
  82         mww 0x31080020 0x093
  83         mdw 0x80020000
  84         mww 0x31080020 0x013
  85
  86         # SYS_CTRL remapping
  87         mww 0x40004014 1
  88 }