tcl/board/propox_mmnet1001.cfg

   1
   2 ## Chip:
   3 set CHIPNAME at91sam9260
   4 set CPUTAPID 0x0792603f
   5 set ENDIAN little
   6 source [find target/at91sam9260.cfg]
   7
   8 $_TARGETNAME configure -event reset-init {at91sam_init}
   9
  10
  11 proc at91sam_init { } {
  12
  13         # at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
  14         jtag_rclk 4
  15
  16         # Enable user reset and disable watchdog
  17         mww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset
  18         mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
  19
  20         # Oscillator setup
  21         mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator (18.432 MHz)
  22         sleep 20                          ;# wait 20 ms
  23         mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
  24         sleep 10                          ;# wait 10 ms
  25
  26         # now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
  27         jtag_rclk 2000
  28
  29         mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
  30         sleep 20                          ;# wait 20 ms
  31         mww 0xfffffc2c 0x207c3f0c         ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
  32         sleep 10                          ;# wait 10 ms
  33         mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler
  34         sleep 10                          ;# wait 10 ms
  35         mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected
  36         sleep 10                          ;# wait 10 ms
  37
  38         # now we are running at 198.656 MHz kHz => full speed jtag
  39         jtag_rclk 30000
  40
  41         arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
  42
  43         # Configure PIO Controller for SDRAM data-lines D16-D31
  44         # PC16-PC31 = Peripheral A: D16-D32
  45         mww 0xfffff844 0xffff0000       ;# Interrupt Disable
  46         mww 0xfffff854 0xffff0000       ;# Multi-Drive Disable
  47         mww 0xfffff860 0xffff0000       ;# Pull-Up Disable
  48         mww 0xfffff870 0xffff0000       ;# PIO_ASR : Select peripheral A function for D15..D31
  49         mww 0xfffff804 0xffff0000       ;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
  50         mww 0xfffffc10 0x00000010       ;# Enable PIO-C Clock in PMC (PID=4)
  51
  52         # SD-Ram setup
  53         mww 0xffffef1c 0x2                      ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
  54         mww 0xffffea08 0x85227259       ;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
  55         mww 0xffffea00 0x1                      ;# SDRAMC_MR : issue a NOP command
  56         mww 0x20000000 0
  57         mww 0xffffea00 0x2                      ;# SDRAMC_MR : issue an 'All Banks Precharge' command
  58         mww 0x20000000 0
  59         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
  60         mww 0x20000000 0
  61         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
  62         mww 0x20000000 0
  63         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
  64         mww 0x20000000 0
  65         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
  66         mww 0x20000000 0
  67         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
  68         mww 0x20000000 0
  69         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
  70         mww 0x20000000 0
  71         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
  72         mww 0x20000000 0
  73         mww 0xffffea00 0x4                      ;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
  74         mww 0x20000000 0
  75         mww 0xffffea00 0x3                      ;# SDRAMC_MR : issue a 'Load Mode Register' command
  76         mww 0x20000000 0
  77         mww 0xffffea00 0x0                      ;# SDRAMC_MR : Normal Mode
  78         mww 0x20000000 0
  79         mww 0xFFFFEA04 0x30d            ;# SDRAM Refresh Time Register
  80                                                                  #  datasheet: 8k refresh cycles / 64 ms
  81                                                                  #  MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
  82
  83 }