tcl/board/pxa255_sst.cfg

   1 # A PXA255 test board with SST 39LF400A flash
   2 #
   3 # At reset the memory map is as follows. Note that
   4 # the memory map changes later on as the application
   5 # starts...
   6 #
   7 # RAM at 0x4000000
   8 # Flash at 0x00000000
   9 #
  10 source [find target/pxa255.cfg]
  11
  12 # Target name is set by above
  13 $_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
  14
  15 # flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
  16 set _FLASHNAME $_CHIPNAME.flash
  17 flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
  18
  19 proc pxa255_sst_init {} {
  20         xscale cp15   15      0x00002001  ;#Enable CP0 and CP13 access
  21         #
  22         # setup GPIO
  23         #
  24         mww    0x40E00018  0x00008000  ;#CPSR0
  25         sleep   20
  26         mww    0x40E0001C  0x00000002  ;#GPSR1
  27         sleep   20
  28         mww    0x40E00020  0x00000008  ;#GPSR2
  29         sleep   20
  30         mww    0x40E0000C  0x00008000  ;#GPDR0
  31         sleep   20
  32         mww    0x40E00054  0x80000000  ;#GAFR0_L
  33         sleep   20
  34         mww    0x40E00058  0x00188010  ;#GAFR0_H
  35         sleep   20
  36         mww    0x40E0005C  0x60908018  ;#GAFR1_L
  37         sleep   20
  38         mww    0x40E0000C  0x0280E000  ;#GPDR0
  39         sleep   20
  40         mww    0x40E00010  0x821C88B2  ;#GPDR1
  41         sleep   20
  42         mww    0x40E00014  0x000F03DB  ;#GPDR2
  43         sleep   20
  44         mww    0x40E00000  0x000F03DB  ;#GPLR0
  45         sleep   20
  46
  47
  48         mww    0x40F00004  0x00000020  ;#PSSR
  49         sleep   20
  50
  51         #
  52         # setup memory controller
  53         #
  54         mww    0x48000008  0x01111998  ;#MSC0
  55         sleep   20
  56         mww    0x48000010  0x00047ff0  ;#MSC2
  57         sleep   20
  58         mww    0x48000014  0x00000000  ;#MECR
  59         sleep   20
  60         mww    0x48000028  0x00010504  ;#MCMEM0
  61         sleep   20
  62         mww    0x4800002C  0x00010504  ;#MCMEM1
  63         sleep   20
  64         mww    0x48000030  0x00010504  ;#MCATT0
  65         sleep   20
  66         mww    0x48000034  0x00010504  ;#MCATT1
  67         sleep   20
  68         mww    0x48000038  0x00004715  ;#MCIO0
  69         sleep   20
  70         mww    0x4800003C  0x00004715  ;#MCIO1
  71         sleep   20
  72         #
  73         mww    0x48000004  0x03CA4018  ;#MDREF
  74         sleep   20
  75         mww    0x48000004  0x004B4018  ;#MDREF
  76         sleep   20
  77         mww    0x48000004  0x000B4018  ;#MDREF
  78         sleep   20
  79         mww    0x48000004  0x000BC018  ;#MDREF
  80         sleep   20
  81         mww    0x48000000  0x00001AC8  ;#MDCNFG
  82         sleep   20
  83
  84         sleep   20
  85
  86         mww    0x48000000  0x00001AC9  ;#MDCNFG
  87         sleep   20
  88         mww    0x48000040  0x00000000  ;#MDMRS
  89         sleep   20
  90 }
  91
  92 $_TARGETNAME configure -event reset-init {pxa255_sst_init}
  93
  94 reset_config trst_and_srst
  95
  96 adapter_nsrst_delay 200
  97 jtag_ntrst_delay 200
  98
  99 #xscale debug_handler 0  0xFFFF0800      ;# debug handler base address