tcl/board/pxa255_sst.cfg

   1 # A PXA255 test board with SST 39LF400A flash
   2 #
   3 # At reset the memory map is as follows. Note that
   4 # the memory map changes later on as the application
   5 # starts...
   6 #
   7 # RAM at 0x4000000
   8 # Flash at 0x00000000
   9 #
  10 source [find target/pxa255.cfg]
  11
  12 # Target name is set by above
  13 $_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
  14
  15 # flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
  16 flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
  17
  18 proc pxa255_sst_init {} {
  19         xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
  20         #
  21         # setup GPIO
  22         #
  23         mww    0x40E00018  0x00008000  #CPSR0
  24         sleep   20
  25         mww    0x40E0001C  0x00000002  #GPSR1
  26         sleep   20
  27         mww    0x40E00020  0x00000008  #GPSR2
  28         sleep   20
  29         mww    0x40E0000C  0x00008000  #GPDR0
  30         sleep   20
  31         mww    0x40E00054  0x80000000  #GAFR0_L
  32         sleep   20
  33         mww    0x40E00058  0x00188010  #GAFR0_H
  34         sleep   20
  35         mww    0x40E0005C  0x60908018  #GAFR1_L
  36         sleep   20
  37         mww    0x40E0000C  0x0280E000  #GPDR0
  38         sleep   20
  39         mww    0x40E00010  0x821C88B2  #GPDR1
  40         sleep   20
  41         mww    0x40E00014  0x000F03DB  #GPDR2
  42         sleep   20
  43         mww    0x40E00000  0x000F03DB  #GPLR0
  44         sleep   20
  45
  46
  47         mww    0x40F00004  0x00000020  #PSSR
  48         sleep   20
  49
  50         #
  51         # setup memory controller
  52         #
  53         mww    0x48000008  0x01111998  #MSC0
  54         sleep   20
  55         mww    0x48000010  0x00047ff0  #MSC2
  56         sleep   20
  57         mww    0x48000014  0x00000000  #MECR
  58         sleep   20
  59         mww    0x48000028  0x00010504  #MCMEM0
  60         sleep   20
  61         mww    0x4800002C  0x00010504  #MCMEM1
  62         sleep   20
  63         mww    0x48000030  0x00010504  #MCATT0
  64         sleep   20
  65         mww    0x48000034  0x00010504  #MCATT1
  66         sleep   20
  67         mww    0x48000038  0x00004715  #MCIO0
  68         sleep   20
  69         mww    0x4800003C  0x00004715  #MCIO1
  70         sleep   20
  71         #
  72         mww    0x48000004  0x03CA4018  #MDREF
  73         sleep   20
  74         mww    0x48000004  0x004B4018  #MDREF
  75         sleep   20
  76         mww    0x48000004  0x000B4018  #MDREF
  77         sleep   20
  78         mww    0x48000004  0x000BC018  #MDREF
  79         sleep   20
  80         mww    0x48000000  0x00001AC8  #MDCNFG
  81         sleep   20
  82
  83         sleep   20
  84
  85         mww    0x48000000  0x00001AC9  #MDCNFG
  86         sleep   20
  87         mww    0x48000040  0x00000000  #MDMRS
  88         sleep   20
  89 }
  90
  91 $_TARGETNAME configure -event reset-init {pxa255_sst_init}
  92
  93 reset_config trst_and_srst
  94
  95 jtag_nsrst_delay 200
  96 jtag_ntrst_delay 200
  97
  98 #xscale debug_handler 0  0xFFFF0800      # debug handler base address