tcl/board/st_b-l475e-iot01a.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip.
   4 # http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html
   5
   6 # This is for using the onboard STLINK
   7 source [find interface/stlink.cfg]
   8
   9 transport select hla_swd
  10
  11 # increase working area to 96KB
  12 set WORKAREASIZE 0x18000
  13
  14 # enable stmqspi
  15 set QUADSPI 1
  16
  17 source [find target/stm32l4x.cfg]
  18
  19 # QUADSPI initialization
  20 proc qspi_init { } {
  21         global a
  22         mmw 0x4002104C 0x000001FF 0                             ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
  23         mmw 0x40021050 0x00000100 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
  24         sleep 1                                                                 ;# Wait for clock startup
  25
  26         # PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
  27
  28         # PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
  29
  30         # Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
  31         mmw 0x48001000 0xAAA00000 0x55500000    ;# MODER
  32         mmw 0x48001008 0xFFF00000 0x00000000    ;# OSPEEDR
  33         mmw 0x48001024 0xAAAAAA00 0x55555500    ;# AFRH
  34
  35         mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  36         mww 0xA0001000 0x01500008                               ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
  37         mww 0xA0001004 0x00160100                               ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
  38         mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
  39
  40         # memory-mapped read mode with 3-byte addresses
  41         mww 0xA0001014 0x0D002503                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
  42 }
  43
  44 $_TARGETNAME configure -event reset-init {
  45         mmw 0x40022000 0x00000004 0x00000003    ;# 4 WS for 72 MHz HCLK
  46         sleep 1
  47         mmw 0x40021000 0x00000100 0x00000000    ;# HSI on
  48         mww 0x4002100C 0x01002432                               ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
  49         mww 0x40021008 0x00008001                               ;# always HSI, APB1: /1, APB2: /1
  50         mmw 0x40021000 0x01000000 0x00000000    ;# PLL on
  51         sleep 1
  52         mmw 0x40021008 0x00000003 0x00000000    ;# switch to PLL
  53         sleep 1
  54
  55         adapter speed 4000
  56
  57         qspi_init
  58 }