tcl/board/stm32f723e-disco.cfg

   1 # This is an STM32F723E discovery board with a single STM32F723IEK6 chip.
   2 # http://www.st.com/en/evaluation-tools/32f723ediscovery.html
   3
   4 # This is for using the onboard STLINK
   5 source [find interface/stlink.cfg]
   6
   7 transport select hla_swd
   8
   9 # increase working area to 128KB
  10 set WORKAREASIZE 0x20000
  11
  12 # enable stmqspi
  13 set QUADSPI 1
  14
  15 source [find target/stm32f7x.cfg]
  16
  17 reset_config srst_only
  18
  19 # QUADSPI initialization
  20 proc qspi_init { } {
  21         global a
  22         mmw 0x40023830 0x000007FF 0                             ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
  23         mmw 0x40023838 0x00000002 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
  24         sleep 1                                                                 ;# Wait for clock startup
  25
  26         # PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
  27
  28         # PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
  29
  30         # Port B: PB06:AF10:V, PB02:AF09:V
  31         mmw 0x40020400 0x00002020 0x00001010    ;# MODER
  32         mmw 0x40020408 0x00003030 0x00000000    ;# OSPEEDR
  33         mmw 0x40020420 0x0A000900 0x05000600    ;# AFRL
  34
  35         # Port C: PC10:AF09:V, PC09:AF09:V
  36         mmw 0x40020800 0x00280000 0x00140000    ;# MODER
  37         mmw 0x40020808 0x003C0000 0x00000000    ;# OSPEEDR
  38         mmw 0x40020824 0x00000990 0x00000660    ;# AFRH
  39
  40         # Port D: PD13:AF09:V
  41         mmw 0x40020C00 0x08000000 0x04000000    ;# MODER
  42         mmw 0x40020C08 0x0C000000 0x00000000    ;# OSPEEDR
  43         mmw 0x40020C24 0x00900000 0x00600000    ;# AFRH
  44
  45         # Port E: PE02:AF09:V
  46         mmw 0x40021000 0x00000020 0x00000010    ;# MODER
  47         mmw 0x40021008 0x00000030 0x00000000    ;# OSPEEDR
  48         mmw 0x40021020 0x00000900 0x00000600    ;# AFRL
  49
  50         mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  51         mww 0xA0001000 0x03500008                               ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
  52         mww 0xA0001004 0x00190100                               ;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
  53         mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
  54
  55         # 1-line spi mode
  56         mww 0xA0001014 0x000003F5                               ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
  57         sleep 1
  58
  59         # memory-mapped read mode with 4-byte addresses
  60         mww 0xA0001014 0x0D003513                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
  61 }
  62
  63 $_TARGETNAME configure -event reset-init {
  64         mww 0x40023C00 0x00000006                               ;# 6 WS for 192 MHz HCLK
  65         sleep 1
  66         mww 0x40023804 0x24003008                               ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
  67         mww 0x40023808 0x00009400                               ;# APB1: /4, APB2: /2
  68         mmw 0x40023800 0x01000000 0x00000000    ;# PLL on
  69         sleep 1
  70         mmw 0x40023808 0x00000002 0x00000000    ;# switch to PLL
  71         sleep 1
  72
  73         adapter speed 4000
  74
  75         qspi_init
  76 }