tcl/board/stm32f723e-disco.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # This is an STM32F723E discovery board with a single STM32F723IEK6 chip.
   4 # http://www.st.com/en/evaluation-tools/32f723ediscovery.html
   5
   6 # This is for using the onboard STLINK
   7 source [find interface/stlink.cfg]
   8
   9 transport select hla_swd
  10
  11 # increase working area to 128KB
  12 set WORKAREASIZE 0x20000
  13
  14 # enable stmqspi
  15 set QUADSPI 1
  16
  17 source [find target/stm32f7x.cfg]
  18
  19 reset_config srst_only
  20
  21 # QUADSPI initialization
  22 proc qspi_init { } {
  23         global a
  24         mmw 0x40023830 0x000007FF 0                             ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
  25         mmw 0x40023838 0x00000002 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
  26         sleep 1                                                                 ;# Wait for clock startup
  27
  28         # PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
  29
  30         # PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
  31
  32         # Port B: PB06:AF10:V, PB02:AF09:V
  33         mmw 0x40020400 0x00002020 0x00001010    ;# MODER
  34         mmw 0x40020408 0x00003030 0x00000000    ;# OSPEEDR
  35         mmw 0x40020420 0x0A000900 0x05000600    ;# AFRL
  36
  37         # Port C: PC10:AF09:V, PC09:AF09:V
  38         mmw 0x40020800 0x00280000 0x00140000    ;# MODER
  39         mmw 0x40020808 0x003C0000 0x00000000    ;# OSPEEDR
  40         mmw 0x40020824 0x00000990 0x00000660    ;# AFRH
  41
  42         # Port D: PD13:AF09:V
  43         mmw 0x40020C00 0x08000000 0x04000000    ;# MODER
  44         mmw 0x40020C08 0x0C000000 0x00000000    ;# OSPEEDR
  45         mmw 0x40020C24 0x00900000 0x00600000    ;# AFRH
  46
  47         # Port E: PE02:AF09:V
  48         mmw 0x40021000 0x00000020 0x00000010    ;# MODER
  49         mmw 0x40021008 0x00000030 0x00000000    ;# OSPEEDR
  50         mmw 0x40021020 0x00000900 0x00000600    ;# AFRL
  51
  52         mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  53         mww 0xA0001000 0x03500008                               ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
  54         mww 0xA0001004 0x00190100                               ;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
  55         mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
  56
  57         # 1-line spi mode
  58         mww 0xA0001014 0x000003F5                               ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
  59         sleep 1
  60
  61         # memory-mapped read mode with 4-byte addresses
  62         mww 0xA0001014 0x0D003513                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
  63 }
  64
  65 $_TARGETNAME configure -event reset-init {
  66         mww 0x40023C00 0x00000006                               ;# 6 WS for 192 MHz HCLK
  67         sleep 1
  68         mww 0x40023804 0x24003008                               ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
  69         mww 0x40023808 0x00009400                               ;# APB1: /4, APB2: /2
  70         mmw 0x40023800 0x01000000 0x00000000    ;# PLL on
  71         sleep 1
  72         mmw 0x40023808 0x00000002 0x00000000    ;# switch to PLL
  73         sleep 1
  74
  75         adapter speed 4000
  76
  77         qspi_init
  78 }