tcl/board/stm32h745i-disco.cfg

   1 # This is a stm32h745i-disco with a single STM32H745XIH6 chip.
   2 # www.st.com/en/product/stm32h745i-disco.html
   3 #
   4
   5 # This is for using the onboard STLINK
   6 source [find interface/stlink.cfg]
   7
   8 transport select hla_swd
   9
  10 set CHIPNAME stm32h745xih6
  11
  12 # enable stmqspi
  13 if {![info exists QUADSPI]} {
  14         set QUADSPI 1
  15 }
  16
  17 source [find target/stm32h7x_dual_bank.cfg]
  18
  19 reset_config srst_only
  20
  21 source [find board/stm32h7x_dual_qspi.cfg]
  22
  23 $_CHIPNAME.cpu0 configure -event reset-init {
  24         global QUADSPI
  25
  26         mmw 0x52002000 0x00000004 0x0000000B    ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
  27
  28         mmw 0x58024400 0x00000001 0x00000018    ;# RCC_CR: HSIDIV=1, HSI on
  29         mmw 0x58024410 0x10000000 0xEE000007    ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
  30         mww 0x58024418 0x00000040                               ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
  31         mww 0x5802441C 0x00000440                               ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
  32         mww 0x58024420 0x00000040                               ;# RCC_D3CFGR: D3PPRE=2
  33         mww 0x58024428 0x00000040                               ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
  34         mmw 0x5802442C 0x0001000C 0x00000002    ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
  35         mww 0x58024430 0x01070217                               ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
  36         mmw 0x58024400 0x01000000 0                             ;# RCC_CR: PLL1ON=1
  37         sleep 1
  38         mmw 0x58024410 0x00000003 0                             ;# RCC_CFGR: PLL1 as system clock
  39         sleep 1
  40
  41         adapter speed 24000
  42
  43         if { $QUADSPI } {
  44                 qspi_init 1
  45         }
  46 }
  47