tcl/board/stm32h7b3i-disco.cfg

   1 # This is a stm32h7b3i-dk with a single STM32H7B3LIH6Q chip.
   2 # https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html
   3 #
   4
   5 # This is for using the onboard STLINK
   6 source [find interface/stlink.cfg]
   7
   8 transport select hla_swd
   9
  10 set CHIPNAME stm32h7b3lih6q
  11
  12 # enable stmqspi
  13 if {![info exists OCTOSPI1]} {
  14         set OCTOSPI1 1
  15         set OCTOSPI2 0
  16 }
  17
  18 source [find target/stm32h7x_dual_bank.cfg]
  19
  20 reset_config srst_only
  21
  22 # OCTOSPI initialization
  23 # octo: 8-line mode
  24 proc octospi_init { octo } {
  25         global a b
  26         mmw 0x58024540 0x000007FF 0                             ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
  27         mmw 0x58024534 0x00284000 0                             ;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
  28         sleep 1                                                                 ;# Wait for clock startup
  29
  30         mww 0x5200B404 0x03010111                               ;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
  31         mww 0x5200B408 0x00000000                               ;# OCTOSPIM_P2CR: disable Port 2
  32
  33         # PG06: OCSPI1_NCS, PB02: OCSPI1_CLK, PC05: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PH03: OCSPI1_IO5,
  34         # PC01: OCSPI1_IO4, PF06: OCSPI1_IO3, PF07: OCSPI1_IO2, PF09: OCSPI1_IO1, PD11: OCSPI1_IO0
  35
  36         # PB02:AF09:V, PC05:AF10:V, PC01:AF10:V, PD11:AF09:V, PD07:AF10:V, PF09:AF10:V
  37         # PF07:AF10:V, PF06:AF10:V, PG09:AF09:V, PG06:AF10:V, PH03:AF09:V
  38         # Port B: PB02:AF09:V
  39         mmw 0x58020400 0x00000020 0x00000010    ;# MODER
  40         mmw 0x58020408 0x00000030 0x00000000    ;# OSPEEDR
  41         mmw 0x5802040C 0x00000000 0x00000030    ;# PUPDR
  42         mmw 0x58020420 0x00000900 0x00000600    ;# AFRL
  43         # Port C: PC05:AF10:V, PC01:AF10:V
  44         mmw 0x58020800 0x00000808 0x00000404    ;# MODER
  45         mmw 0x58020808 0x00000C0C 0x00000000    ;# OSPEEDR
  46         mmw 0x5802080C 0x00000000 0x00000C0C    ;# PUPDR
  47         mmw 0x58020820 0x00A000A0 0x00500050    ;# AFRL
  48         # Port D: PD11:AF09:V, PD07:AF10:V
  49         mmw 0x58020C00 0x00808000 0x00404000    ;# MODER
  50         mmw 0x58020C08 0x00C0C000 0x00000000    ;# OSPEEDR
  51         mmw 0x58020C0C 0x00000000 0x00C0C000    ;# PUPDR
  52         mmw 0x58020C20 0xA0000000 0x50000000    ;# AFRL
  53         mmw 0x58020C24 0x00009000 0x00006000    ;# AFRH
  54         # Port F: PF09:AF10:V, PF07:AF10:V, PF06:AF10:V
  55         mmw 0x58021400 0x0008A000 0x00045000    ;# MODER
  56         mmw 0x58021408 0x000CF000 0x00000000    ;# OSPEEDR
  57         mmw 0x5802140C 0x00000000 0x000CF000    ;# PUPDR
  58         mmw 0x58021420 0xAA000000 0x55000000    ;# AFRL
  59         mmw 0x58021424 0x000000A0 0x00000050    ;# AFRH
  60         # Port G: PG09:AF09:V, PG06:AF10:V
  61         mmw 0x58021800 0x00082000 0x00041000    ;# MODER
  62         mmw 0x58021808 0x000C3000 0x00000000    ;# OSPEEDR
  63         mmw 0x5802180C 0x00000000 0x000C3000    ;# PUPDR
  64         mmw 0x58021820 0x0A000000 0x05000000    ;# AFRL
  65         mmw 0x58021824 0x00000090 0x00000060    ;# AFRH
  66         # Port H: PH03:AF09:V
  67         mmw 0x58021C00 0x00000080 0x00000040    ;# MODER
  68         mmw 0x58021C08 0x000000C0 0x00000000    ;# OSPEEDR
  69         mmw 0x58021C0C 0x00000000 0x000000C0    ;# PUPDR
  70         mmw 0x58021C20 0x00009000 0x00006000    ;# AFRL
  71
  72         # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
  73         mww 0x52005130 0x00001000                               ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  74         mww 0x52005000 0x3040000B                               ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
  75         mww 0x52005008 0x01190100                               ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
  76         mww 0x5200500C 0x00000005                               ;# OCTOSPI_DCR2: PRESCALER=5
  77
  78         mww 0x52005108 0x00000000                               ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
  79         mww 0x52005100 0x01003101                               ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
  80         mww 0x52005110 0x00000013                               ;# OCTOSPI_IR: INSTR=READ4B
  81
  82         flash probe $a                                                  ;# load configuration from CR, TCR, CCR, IR register values
  83
  84         if { $octo == 1 } {
  85                 stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00                       ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
  86                 stmqspi cmd $a 0 0x06                                                           ;# Write Enable
  87                 stmqspi cmd $a 1 0x05                                                           ;# Read Status Register
  88                 stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02          ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
  89
  90                 # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
  91                 mww 0x52005000 0x3040000B                               ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
  92                 mww 0x52005108 0x10000006                               ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
  93                 mww 0x52005100 0x2C003C1C                               ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
  94                 mww 0x52005110 0x0000EE11                               ;# OCTOSPI_IR: INSTR=OCTA DTR Read
  95
  96                 flash probe $a                                                  ;# reload configuration from CR, TCR, CCR, IR register values
  97
  98                 stmqspi cmd $a 0 0x06                                                           ;# Write Enable
  99                 stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00                       ;# Read Status Register (note dummy address in 8-line mode)
 100                 stmqspi cmd $a 0 0x04                                                           ;# Write Disable
 101                 stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00                       ;# Read Status Register (note dummy address in 8-line mode)
 102                 stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00                       ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
 103         }
 104 }
 105
 106 $_CHIPNAME.cpu0 configure -event reset-init {
 107         global OCTOSPI1
 108         global OCTOSPI2
 109
 110         mmw 0x52002000 0x00000004 0x0000000B    ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
 111
 112         mmw 0x58024400 0x00000001 0x00000018    ;# RCC_CR: HSIDIV=1, HSI on
 113         mmw 0x58024410 0x10000000 0xEE000007    ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
 114         mww 0x58024418 0x00000040                               ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
 115         mww 0x5802441C 0x00000440                               ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
 116         mww 0x58024420 0x00000040                               ;# RCC_D3CFGR: D3PPRE=2
 117         mww 0x58024428 0x00000040                               ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
 118         mmw 0x5802442C 0x0001000C 0x00000002    ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
 119         mww 0x58024430 0x01070217                               ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
 120         mmw 0x58024400 0x01000000 0                             ;# RCC_CR: PLL1ON=1
 121         sleep 1
 122         mmw 0x58024410 0x00000003 0                             ;# RCC_CFGR: PLL1 as system clock
 123         sleep 1
 124
 125         adapter speed 24000
 126
 127         if { $OCTOSPI1 } {
 128                 octospi_init 1
 129         }
 130 }