tcl/board/stm32l496g-disco.cfg

   1 # This is an STM32L496G discovery board with a single STM32L496AGI6 chip.
   2 # http://www.st.com/en/evaluation-tools/32l496gdiscovery.html
   3
   4 # This is for using the onboard STLINK
   5 source [find interface/stlink.cfg]
   6
   7 transport select hla_swd
   8
   9 # increase working area to 96KB
  10 set WORKAREASIZE 0x18000
  11
  12 # enable stmqspi
  13 set QUADSPI 1
  14
  15 source [find target/stm32l4x.cfg]
  16
  17 # QUADSPI initialization
  18 proc qspi_init { } {
  19         global a
  20         mmw 0x4002104C 0x000001FF 0                             ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
  21         mmw 0x40021050 0x00000100 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
  22         sleep 1                                                                 ;# Wait for clock startup
  23
  24         # PB11: BK1_NCS, PA03: CLK, PA06: BK1_IO3, PA07: BK1_IO2, PB00: BK1_IO1, PB01: BK1_IO0
  25
  26         # PA07:AF10:V, PA06:AF10:V, PA03:AF10:V, PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
  27
  28         # Port A: PA07:AF10:V, PA06:AF10:V, PA03:AF10:V
  29         mmw 0x48000000 0x0000A080 0x00005040    ;# MODER
  30         mmw 0x48000008 0x0000F0C0 0x00000000    ;# OSPEEDR
  31         mmw 0x48000020 0xAA00A000 0x55005000    ;# AFRL
  32
  33         # Port B: PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
  34         mmw 0x48000400 0x0080000A 0x00400005    ;# MODER
  35         mmw 0x48000408 0x00C0000F 0x00000000    ;# OSPEEDR
  36         mmw 0x48000420 0x000000AA 0x00000055    ;# AFRL
  37         mmw 0x48000424 0x0000A000 0x00005000    ;# AFRH
  38
  39         mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  40         mww 0xA0001000 0x01500008                               ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
  41         mww 0xA0001004 0x00160100                               ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
  42         mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
  43
  44         # 1-line spi mode
  45         mww 0xA0001014 0x000003F5                               ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
  46         sleep 1
  47
  48         # memory-mapped read mode with 3-byte addresses
  49         mww 0xA0001014 0x0D002503                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
  50 }
  51
  52 $_TARGETNAME configure -event reset-init {
  53         mmw 0x40022000 0x00000004 0x00000003    ;# 4 WS for 72 MHz HCLK
  54         sleep 1
  55         mmw 0x40021000 0x00000100 0x00000000    ;# HSI on
  56         mww 0x4002100C 0x01002432                               ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
  57         mww 0x40021008 0x00008001                               ;# always HSI, APB1: /1, APB2: /1
  58         mmw 0x40021000 0x01000000 0x00000000    ;# PLL on
  59         sleep 1
  60         mmw 0x40021008 0x00000003 0x00000000    ;# switch to PLL
  61         sleep 1
  62
  63         adapter speed 4000
  64
  65         qspi_init
  66 }