tcl/board/tp-link_tl-mr3020.cfg

   1 source [find target/atheros_ar9331.cfg]
   2
   3 proc ar9331_25mhz_pll_init {} {
   4         mww 0xb8050008 0x00018004       ;# bypass PLL; AHB_POST_DIV - ratio 4
   5         mww 0xb8050004 0x00000352       ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
   6         mww 0xb8050000 0x40818000       ;# Power down control for CPU PLL
   7                                         ;# OUTDIV | REFDIV | DIV_INT
   8         mww 0xb8050010 0x001003e8       ;# CPU PLL Dither FRAC Register
   9                                         ;# (disabled?)
  10         mww 0xb8050000 0x00818000       ;# Power on | OUTDIV | REFDIV | DIV_INT
  11         mww 0xb8050008 0x00008000       ;# remove bypass;
  12                                         ;# AHB_POST_DIV - ratio 2
  13 }
  14
  15 proc ar9331_ddr1_init {} {
  16         mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
  17         mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
  18
  19         mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
  20         mww 0xb8000008 0x133    ;# mode reg: 0x133 - default
  21         mww 0xb8000010 0x1      ;# Forces an MRS update cycl
  22         mww 0xb800000c 0x2      ;# Extended mode register value.
  23                                 ;# default 0x2 - Reset to weak driver, DLL on
  24         mww 0xb8000010 0x2      ;# Forces an EMRS update cycle
  25         mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
  26         mww 0xb8000008 0x33     ;# mode reg: remove some bit?
  27         mww 0xb8000010 0x1      ;# Forces an MRS update cycl
  28         mww 0xb8000014 0x4186   ;# enable refres: bit(14) - set refresh rate
  29         mww 0xb800001c 0x8      ;# This register is used along with DQ Lane 0,
  30                                 ;# DQ[7:0], DQS_0
  31         mww 0xb8000020 0x9      ;# This register is used along with DQ Lane 1,
  32                                 ;# DQ[15:8], DQS_1.
  33         mww 0xb8000018 0xff     ;# DDR read and capture bit mask.
  34                                 ;# Each bit represents a cycle of valid data.
  35 }
  36
  37 $_TARGETNAME configure -event reset-init {
  38         ar9331_25mhz_pll_init
  39         sleep 1
  40         ar9331_ddr1_init
  41 }
  42
  43 set ram_boot_address 0xa0000000
  44 $_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
  45
  46 flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0