1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Cadence virtual debug interface
3 # Arm Cortex m4 through JTAG
5 source [find interface/vdebug.cfg]
8 set _MEMSTART 0x00000000
10 set _CPUTAPID 0x4ba00477
12 # vdebug select transport
13 #transport select jtag
15 # JTAG reset config, frequency and reset delay
16 reset_config trst_and_srst
20 # BFM hierarchical path and input clk period
21 vdebug bfm_path tbench.u_vd_jtag_bfm 20ns
23 # DMA Memories to access backdoor (up to 4)
24 vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
26 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
30 source [find target/vd_cortex_m.cfg]
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