1 # SPDX-License-Identifier: GPL-2.0-or-later
3 uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
4 uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
5 uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
6 uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
7 uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
9 proc at91sam9_reset_start { } {
11 arm7_9 fast_memory_access disable
16 set rstc_mr_val $::AT91_RSTC_KEY
17 set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
18 set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
19 mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
22 proc at91sam9_reset_init { config } {
24 mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog
26 set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
28 mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
29 while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
31 set pllar_val $::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
32 set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}]
33 set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
34 set pllar_val [expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
35 set pllar_val [expr {$pllar_val | $config(master_pll_div)}]
37 mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
38 while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
40 ;# PCK/2 = MCK Master Clock from PLLA
41 set mckr_val $::AT91_PMC_CSS_PLLA
42 set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}]
43 set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
44 set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}]
46 mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
47 while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
49 ## switch JTAG clock to highspeed clock
52 arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
53 arm7_9 fast_memory_access enable
55 set rstc_mr_val $::AT91_RSTC_KEY
56 set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
57 mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
59 if { [info exists config(sdram_piod)] } {
60 set pdr_addr [expr {$::AT91_PIOD + $::PIO_PDR}]
61 set pudr_addr [expr {$::AT91_PIOD + $::PIO_PUDR}]
62 set asr_addr [expr {$::AT91_PIOD + $::PIO_ASR}]
63 mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
64 mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
65 mww $asr_addr 0xffff0000
67 set pdr_addr [expr {$::AT91_PIOC + $::PIO_PDR}]
68 set pudr_addr [expr {$::AT91_PIOC + $::PIO_PUDR}]
69 mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
70 mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
73 mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
74 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register
75 mww $::AT91_SDRAMC_TR $config(sdram_tr_val) ;# SDRAMC_TR - Refresh Timer register
76 mww $::AT91_SDRAMC_CR $config(sdram_cr_val) ;# SDRAMC_CR - Configuration register
77 mww $::AT91_SDRAMC_MDR $::AT91_SDRAMC_MD_SDRAM ;# Memory Device Register -> SDRAM
78 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_PRECHARGE ;# SDRAMC_MR
79 mww $config(sdram_base) 0 ;# SDRAM_BASE
80 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_REFRESH ;# SDRC_MR
81 mww $config(sdram_base) 0 ;# SDRAM_BASE
82 mww $config(sdram_base) 0 ;# SDRAM_BASE
83 mww $config(sdram_base) 0 ;# SDRAM_BASE
84 mww $config(sdram_base) 0 ;# SDRAM_BASE
85 mww $config(sdram_base) 0 ;# SDRAM_BASE
86 mww $config(sdram_base) 0 ;# SDRAM_BASE
87 mww $config(sdram_base) 0 ;# SDRAM_BASE
88 mww $config(sdram_base) 0 ;# SDRAM_BASE
89 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_LMR ;# SDRC_MR
90 mww $config(sdram_base) 0 ;# SDRAM_BASE
91 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRC_MR
92 mww $config(sdram_base) 0 ;# SDRAM_BASE
93 mww $::AT91_SDRAMC_TR 1200 ;# SDRAM_TR
94 mww $config(sdram_base) 0 ;# SDRAM_BASE
96 mww $::AT91_MATRIX 0xf ;# MATRIX_MCFG - REMAP all masters