tcl/chip/ti/lm3s/lm3s_regs.tcl

   1 #*****************************************************************************
   2 #
   3 # The following are defines for the System Control register addresses.
   4 #
   5 #*****************************************************************************
   6
   7 set SYSCTL_DID0             0x400FE000  ;# Device Identification 0
   8 set SYSCTL_DID1             0x400FE004  ;# Device Identification 1
   9 set SYSCTL_DC0              0x400FE008  ;# Device Capabilities 0
  10 set SYSCTL_DC1              0x400FE010  ;# Device Capabilities 1
  11 set SYSCTL_DC2              0x400FE014  ;# Device Capabilities 2
  12 set SYSCTL_DC3              0x400FE018  ;# Device Capabilities 3
  13 set SYSCTL_DC4              0x400FE01C  ;# Device Capabilities 4
  14 set SYSCTL_DC5              0x400FE020  ;# Device Capabilities 5
  15 set SYSCTL_DC6              0x400FE024  ;# Device Capabilities 6
  16 set SYSCTL_DC7              0x400FE028  ;# Device Capabilities 7
  17 set SYSCTL_DC8              0x400FE02C  ;# Device Capabilities 8 ADC
  18                                         ;# Channels
  19 set SYSCTL_PBORCTL          0x400FE030  ;# Brown-Out Reset Control
  20 set SYSCTL_LDOPCTL          0x400FE034  ;# LDO Power Control
  21 set SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0
  22 set SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1
  23 set SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2
  24 set SYSCTL_RIS              0x400FE050  ;# Raw Interrupt Status
  25 set SYSCTL_IMC              0x400FE054  ;# Interrupt Mask Control
  26 set SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and
  27                                         ;# Clear
  28 set SYSCTL_RESC             0x400FE05C  ;# Reset Cause
  29 set SYSCTL_RCC              0x400FE060  ;# Run-Mode Clock Configuration
  30 set SYSCTL_PLLCFG           0x400FE064  ;# XTAL to PLL Translation
  31 set SYSCTL_GPIOHSCTL        0x400FE06C  ;# GPIO High-Speed Control
  32 set SYSCTL_GPIOHBCTL        0x400FE06C  ;# GPIO High-Performance Bus
  33                                         ;# Control
  34 set SYSCTL_RCC2             0x400FE070  ;# Run-Mode Clock Configuration 2
  35 set SYSCTL_MOSCCTL          0x400FE07C  ;# Main Oscillator Control
  36 set SYSCTL_RCGC0            0x400FE100  ;# Run Mode Clock Gating Control
  37                                         ;# Register 0
  38 set SYSCTL_RCGC1            0x400FE104  ;# Run Mode Clock Gating Control
  39                                         ;# Register 1
  40 set SYSCTL_RCGC2            0x400FE108  ;# Run Mode Clock Gating Control
  41                                         ;# Register 2
  42 set SYSCTL_SCGC0            0x400FE110  ;# Sleep Mode Clock Gating Control
  43                                         ;# Register 0
  44 set SYSCTL_SCGC1            0x400FE114  ;# Sleep Mode Clock Gating Control
  45                                         ;# Register 1
  46 set SYSCTL_SCGC2            0x400FE118  ;# Sleep Mode Clock Gating Control
  47                                         ;# Register 2
  48 set SYSCTL_DCGC0            0x400FE120  ;# Deep Sleep Mode Clock Gating
  49                                         ;# Control Register 0
  50 set SYSCTL_DCGC1            0x400FE124  ;# Deep-Sleep Mode Clock Gating
  51                                         ;# Control Register 1
  52 set SYSCTL_DCGC2            0x400FE128  ;# Deep Sleep Mode Clock Gating
  53                                         ;# Control Register 2
  54 set SYSCTL_DSLPCLKCFG       0x400FE144  ;# Deep Sleep Clock Configuration
  55 set SYSCTL_CLKVCLR          0x400FE150  ;# Clock Verification Clear
  56 set SYSCTL_PIOSCCAL         0x400FE150  ;# Precision Internal Oscillator
  57                                         ;# Calibration
  58 set SYSCTL_PIOSCSTAT        0x400FE154  ;# Precision Internal Oscillator
  59                                         ;# Statistics
  60 set SYSCTL_LDOARST          0x400FE160  ;# Allow Unregulated LDO to Reset
  61                                         ;# the Part
  62 set SYSCTL_I2SMCLKCFG       0x400FE170  ;# I2S MCLK Configuration
  63 set SYSCTL_DC9              0x400FE190  ;# Device Capabilities 9 ADC
  64                                         ;# Digital Comparators
  65 set SYSCTL_NVMSTAT          0x400FE1A0  ;# Non-Volatile Memory Information
  66
  67 set SYSCTL_RCC_USESYSDIV    0x00400000  ;# Enable System Clock Divider
  68 set SYSCTL_RCC2_BYPASS2     0x00000800  ;# PLL Bypass 2
  69 set SYSCTL_RCC_MOSCDIS      0x00000001  ;# Main Oscillator Disable
  70
  71 set SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0
  72 set SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1
  73 set SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2
  74
  75 set SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and Clear
  76
  77 set FLASH_FMA               0x400FD000  ;# Flash Memory Address
  78 set FLASH_FMD               0x400FD004  ;# Flash Memory Data
  79 set FLASH_FMC               0x400FD008  ;# Flash Memory Control
  80 set FLASH_FCRIS             0x400FD00C  ;# Flash Controller Raw Interrupt Status
  81 set FLASH_FCIM              0x400FD010  ;# Flash Controller Interrupt Mask
  82 set FLASH_FCMISC            0x400FD014  ;# Flash Controller Masked Interrupt Status and Clear
  83 set FLASH_FMC2              0x400FD020  ;#  Flash Memory Control 2
  84 set FLASH_FWBVAL            0x400FD030  ;# Flash Write Buffer Valid