tcl/memory.tcl

   1 # MEMORY
   2 #
   3 # All Memory regions have two components.
   4 #    (1) A count of regions, in the form N_NAME
   5 #    (2) An array within info about each region.
   6 #
   7 # The ARRAY
   8 #
   9 #       <NAME>(  RegionNumber ,  ATTRIBUTE )
  10 #
  11 # Where <NAME> is one of:
  12 #
  13 #     N_FLASH  & FLASH   (internal memory)
  14 #     N_RAM    & RAM     (internal memory)
  15 #     N_MMREGS & MMREGS  (for memory mapped registers)
  16 #     N_XMEM   & XMEM    (off chip memory, ie: flash on cs0, sdram on cs2)
  17 # or  N_UNKNOWN & UNKNOWN for things that do not exist.
  18 #
  19 # We have 1 unknown region.
  20 set N_UNKNOWN 1
  21 # All MEMORY regions must have these attributes
  22 #     CS          - chip select (if internal, use -1)
  23 set UNKNOWN(0,CHIPSELECT) -1
  24 #     BASE        - base address in memory
  25 set UNKNOWN(0,BASE)       0
  26 #     LEN         - length in bytes
  27 set UNKNOWN(0,LEN)        $CPU_MAX_ADDRESS
  28 #     HUMAN       - human name of the region
  29 set UNKNOWN(0,HUMAN) "unknown"
  30 #     TYPE        - one of:
  31 #                       flash, ram, mmr, unknown
  32 #                    For harvard arch:
  33 #                       iflash, dflash, iram, dram
  34 set UNKNOWN(0,TYPE)       "unknown"
  35 #     RWX         - access ablity
  36 #                       unix style chmod bits
  37 #                           0 - no access
  38 #                           1 - execute
  39 #                           2 - write
  40 #                           4 - read
  41 #                       hence: 7 - readwrite execute
  42 set RWX_NO_ACCESS     0
  43 set RWX_X_ONLY        $BIT0
  44 set RWX_W_ONLY        $BIT1
  45 set RWX_R_ONLY        $BIT2
  46 set RWX_RW            [expr {$RWX_R_ONLY + $RWX_W_ONLY}]
  47 set RWX_R_X           [expr {$RWX_R_ONLY + $RWX_X_ONLY}]
  48 set RWX_RWX           [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]
  49 set UNKNOWN(0,RWX)     $RWX_NO_ACCESS
  50
  51 #     WIDTH       - access width
  52 #                      8,16,32 [0 means ANY]
  53 set ACCESS_WIDTH_NONE 0
  54 set ACCESS_WIDTH_8    $BIT0
  55 set ACCESS_WIDTH_16   $BIT1
  56 set ACCESS_WIDTH_32   $BIT2
  57 set ACCESS_WIDTH_ANY  [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]
  58 set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
  59
  60 proc iswithin { ADDRESS BASE LEN } {
  61     return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
  62 }
  63
  64 proc address_info { ADDRESS } {
  65
  66     foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
  67         if { info exists $WHERE } {
  68             set lmt [set N_[set WHERE]]
  69             for { set region 0 } { $region < $lmt } { incr region } {
  70                 if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {
  71                     return  "$WHERE $region";
  72                 }
  73             }
  74         }
  75     }
  76
  77     # Return the 'unknown'
  78     return "UNKNOWN 0"
  79 }
  80
  81 proc memread32 {ADDR} {
  82     if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] {
  83         return $foo
  84     } else {
  85         error "memread32: $msg"
  86     }
  87 }
  88
  89 proc memread16 {ADDR} {
  90     if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] {
  91         return $foo
  92     } else {
  93         error "memread16: $msg"
  94     }
  95 }
  96
  97 proc memread8 {ADDR} {
  98     if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] {
  99         return $foo
 100     } else {
 101         error "memread8: $msg"
 102     }
 103 }
 104
 105 proc memwrite32 {ADDR DATA} {
 106     if ![ catch { write_memory $ADDR 32 $DATA } msg ] {
 107         return $DATA
 108     } else {
 109         error "memwrite32: $msg"
 110     }
 111 }
 112
 113 proc memwrite16 {ADDR DATA} {
 114     if ![ catch { write_memory $ADDR 16 $DATA } msg ] {
 115         return $DATA
 116     } else {
 117         error "memwrite16: $msg"
 118     }
 119 }
 120
 121 proc memwrite8 {ADDR DATA} {
 122     if ![ catch { write_memory $ADDR 8 $DATA } msg ] {
 123         return $DATA
 124     } else {
 125         error "memwrite8: $msg"
 126     }
 127 }
 128
 129 proc memread32_phys {ADDR} {
 130     if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] {
 131         return $foo
 132     } else {
 133         error "memread32: $msg"
 134     }
 135 }
 136
 137 proc memread16_phys {ADDR} {
 138     if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] {
 139         return $foo
 140     } else {
 141         error "memread16: $msg"
 142     }
 143 }
 144
 145 proc memread8_phys {ADDR} {
 146     if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] {
 147         return $foo
 148     } else {
 149         error "memread8: $msg"
 150     }
 151 }
 152
 153 proc memwrite32_phys {ADDR DATA} {
 154     if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] {
 155         return $DATA
 156     } else {
 157         error "memwrite32: $msg"
 158     }
 159 }
 160
 161 proc memwrite16_phys {ADDR DATA} {
 162     if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] {
 163         return $DATA
 164     } else {
 165         error "memwrite16: $msg"
 166     }
 167 }
 168
 169 proc memwrite8_phys {ADDR DATA} {
 170     if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] {
 171         return $DATA
 172     } else {
 173         error "memwrite8: $msg"
 174     }
 175 }