stm32f30x: Add boundary scan TAP ID to match silicon
[openocd.git] / tcl / target / aduc702x.cfg
1 if { [info exists CHIPNAME] } {
2 set _CHIPNAME $CHIPNAME
3 } else {
4 set _CHIPNAME aduc702x
5 }
6
7 if { [info exists ENDIAN] } {
8 set _ENDIAN $ENDIAN
9 } else {
10 # This config file was defaulting to big endian..
11 set _ENDIAN little
12 }
13
14 if { [info exists CPUTAPID] } {
15 set _CPUTAPID $CPUTAPID
16 } else {
17 set _CPUTAPID 0x3f0f0f0f
18 }
19
20 adapter_nsrst_delay 200
21 jtag_ntrst_delay 200
22
23 ## JTAG scan chain
24 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
25 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
26
27 ##
28 ## Target configuration
29 ##
30 set _TARGETNAME $_CHIPNAME.cpu
31 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
32
33 # allocate the entire SRAM as working area
34 $_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
35
36 ## flash configuration
37 # only target number is needed
38 set _FLASHNAME $_CHIPNAME.flash
39 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
40
41 ## If you use the watchdog, the following code makes sure that the board
42 ## doesn't reboot when halted via JTAG. Yes, on the older generation
43 ## AdUC702x, timer3 continues running even when the CPU is halted.
44
45 proc watchdog_service {} {
46 global watchdog_hdl
47 mww 0xffff036c 0
48 # echo "watchdog!!"
49 set watchdog_hdl [after 500 watchdog_service]
50 }
51
52 $_TARGETNAME configure -event reset-halt-post { watchdog_service }
53 $_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl }

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)