Fix spelling of ARM Cortex
[openocd.git] / tcl / target / altera_fpgasoc.cfg
1 #
2 # Altera cyclone V SoC family, 5Cxxx
3 #
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
6 } else {
7 set _CHIPNAME fpgasoc
8 }
9
10 # CoreSight Debug Access Port
11 if { [info exists DAP_TAPID] } {
12 set _DAP_TAPID $DAP_TAPID
13 } else {
14 set _DAP_TAPID 0x4ba00477
15 }
16
17 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
18 -expected-id $_DAP_TAPID
19
20 # Subsidiary TAP: fpga
21 if { [info exists FPGA_TAPID] } {
22 set _FPGA_TAPID $FPGA_TAPID
23 } else {
24 set _FPGA_TAPID 0x02d020dd
25 }
26 jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
27
28
29 #
30 # Cortex-A9 target
31 #
32
33 # GDB target: Cortex-A9, using DAP, configuring only one core
34 # Base addresses of cores:
35 # core 0 - 0x80110000
36 # core 1 - 0x80112000
37
38 # Slow speed to be sure it will work
39 adapter_khz 1000
40
41 set _TARGETNAME1 $_CHIPNAME.cpu.0
42 set _TARGETNAME2 $_CHIPNAME.cpu.1
43
44 # A9 core 0
45 target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
46 -coreid 0 -dbgbase 0x80110000
47
48 $_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
49 $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
50 $_TARGETNAME1 configure -event gdb-attach { halt }
51
52
53 # A9 core 1
54 #target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
55 # -coreid 1 -dbgbase 0x80112000
56
57 #$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
58 #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
59 #$_TARGETNAME2 configure -event gdb-attach { halt }
60
61 proc cycv_dbginit {target} {
62 # General Cortex-A8/A9 debug initialisation
63 cortex_a dbginit
64 }

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