target: rename cortex_a8 to cortex_a
[openocd.git] / tcl / target / amdm37x.cfg
1 #
2 # Copyright (C) 2010-2011 by Karl Kurbjun
3 # Copyright (C) 2009-2011 by √ėyvind Harboe
4 # Copyright (C) 2009 by David Brownell
5 # Copyright (C) 2009 by Magnus Lundin
6 #
7 # TI AM/DM37x
8 # http://www.ti.com/litv/pdf/sprugn4b
9 #
10 # This script is based on the AM3517 initialization. It should be considered
11 # preliminary since it needs more complete testing and only the basic
12 # operations work.
13 #
14
15 ###############################################################################
16 # User modifiable parameters
17 ###############################################################################
18
19 # This script uses the variable CHIPTYPE to determine whether this is an AM35x
20 # or DM37x target. If CHIPTYPE is not set it will error out.
21 if { [info exists CHIPTYPE] } {
22
23 if { [info exists CHIPNAME] } {
24 set _CHIPNAME $CHIPNAME
25 } else {
26 set _CHIPNAME $CHIPTYPE
27 }
28
29 switch $CHIPTYPE {
30 dm37x {
31 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
32 set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
33 }
34 am35x {
35 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
36 set _JRC_TAPID "-expected-id 0x0b7ae02f"
37 }
38 default {
39 error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
40 }
41 }
42 } else {
43 error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
44 }
45
46 # Run the adapter at the fastest acceptable speed with the slowest possible
47 # core clock.
48 adapter_khz 10
49
50 ###############################################################################
51 # JTAG setup
52 # The OpenOCD commands are described in the TAP Declaration section
53 # http://openocd.berlios.de/doc/html/TAP-Declaration.html
54 ###############################################################################
55
56 # The AM/DM37x has an ICEpick module in it like many of TI's other devices. More
57 # can be read about this module in sprugn4b under chapter 27: "Debug and
58 # Emulation". The module is used to route the JTAG chain to the various
59 # subsystems in the chip.
60 source [find target/icepick.cfg]
61
62 # The TAP order should be described from the TDO connection in OpenOCD to the
63 # TDI pin. The OpenOCD FAQ describes this in more detail:
64 # http://openocd.berlios.de/doc/html/FAQ.html
65
66 # From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO:
67 #
68 # Device | TAP number
69 # ---------|------------
70 # DAP | 3
71 # Sequencer| 2 Note: The sequencer is an ARM968
72 # DSP | 1
73 # D2D | 0
74 #
75 # Right now the only secondary tap enabled is the DAP so the rest are left
76 # undescribed.
77
78 ######
79 # Start of Chain Description
80 # The Secondary TAPs all have enable functions defined for use with the ICEpick
81 # Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
82 # the TAP numbers for ICEpick do not change.
83 #
84 # TODO: A disable function should also be added.
85 ######
86
87 # Secondary TAP: DAP is closest to the TDO output
88 # The TAP enable event also needs to be described
89 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
90 jtag configure $_CHIPNAME.dap -event tap-enable \
91 "icepick_c_tapenable $_CHIPNAME.jrc 3"
92
93 # These taps are only present in the DM37x series.
94 if { $CHIPTYPE == "dm37x" } {
95 # Secondary TAP: Sequencer (ARM968) it is not in the chain by default
96 # The ICEpick can be used to enable it in the chain.
97 jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
98 jtag configure $_CHIPNAME.arm2 -event tap-enable \
99 "icepick_c_tapenable $_CHIPNAME.jrc 2"
100
101 # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
102 # The ICEpick can be used to enable it in the chain.
103 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
104 jtag configure $_CHIPNAME.dsp -event tap-enable \
105 "icepick_c_tapenable $_CHIPNAME.jrc 1"
106 }
107
108 # Secondary TAP: D2D it is not in the chain by default (-disable)
109 # The ICEpick can be used to enable it in the chain.
110 # This IRLEN is probably incorrect - not sure where the documentation is.
111 jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
112 jtag configure $_CHIPNAME.d2d -event tap-enable \
113 "icepick_c_tapenable $_CHIPNAME.jrc 0"
114
115 # Primary TAP: ICEpick - it is closest to TDI so last in the chain
116 eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
117
118 ######
119 # End of Chain Description
120 ######
121
122 ######
123 # Start JTAG TAP events
124 ######
125
126 # some TCK tycles are required to activate the DEBUG power domain
127 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
128
129 # Enable the DAP TAP
130 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
131
132 ######
133 # End JTAG TAP events
134 ######
135
136 ###############################################################################
137 # Target Setup:
138 # This section is described in the OpenOCD documentation under CPU Configuration
139 # http://openocd.berlios.de/doc/html/CPU-Configuration.html
140 ###############################################################################
141
142 # Create the CPU target to be used with GDB: Cortex-A8, using DAP
143 set _TARGETNAME $_CHIPNAME.cpu
144 target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
145
146 # The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
147 # 16K to be used as a scratchpad for OpenOCD.
148
149 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
150
151 ######
152 # Start Target Reset Event Setup:
153 ######
154
155 # Set the JTAG clock down to 10 kHz to be sure that it will work with the
156 # slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
157 # *after* PLL and clock tree setup.
158
159 $_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
160
161 # Describe the reset assert process for openocd - this is asserted with the
162 # ICEPick
163 $_TARGETNAME configure -event "reset-assert" {
164
165 global _CHIPNAME
166
167 # assert warm system reset through ICEPick
168 icepick_c_wreset $_CHIPNAME.jrc
169 }
170
171 # After the reset is asserted we need to re-initialize debugging and speed up
172 # the JTAG clock.
173
174 $_TARGETNAME configure -event reset-assert-post {
175
176 global _TARGETNAME
177 amdm37x_dbginit $_TARGETNAME
178 adapter_khz 1000
179 }
180
181 $_TARGETNAME configure -event gdb-attach {
182
183 global _TARGETNAME
184 amdm37x_dbginit $_TARGETNAME
185
186 echo "Halting target"
187 halt
188 }
189
190 ######
191 # End Target Reset Event Setup:
192 ######
193
194 ###############################################################################
195 # Target Functions
196 # Add any functions needed for the target here
197 ###############################################################################
198
199 # Run this to enable invasive debugging. This is run automatically in the
200 # reset sequence.
201 proc amdm37x_dbginit {target} {
202 # General Cortex A8 debug initialisation
203 cortex_a dbginit
204
205 # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
206 # access to the signal appears to be implementation specific. TI does not
207 # describe this register much except a quick line that states DBGEM (sic) is
208 # at this address and this bit.
209 $target mww phys 0x5401d030 0x00002000
210 }
211

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)