tcl/target/ampere_qs_mq.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 #
   3 # OpenOCD Target Configuration for Ampere Altra ("Quicksilver") and
   4 # Ampere Altra Max ("Mystique") processors
   5 #
   6 # Copyright (c) 2019-2022, Ampere Computing LLC
   7
   8 # Command Line Argument Description
   9 #
  10 # SPLITSMP
  11 # Only used for dual socket systems. Do not use for a single socket setup.
  12 # Option pertains to the ARMv8 target core naming in a dual socket setup.
  13 # If specified, name all ARMv8 cores per socket as individual SMP sessions.
  14 # If not specified, name ARMv8 cores from both sockets as one SMP session.
  15 # This option is used in conjunction with the SMP_STR board file option.
  16 # Syntax: -c "set SPLITSMP {}"
  17 #
  18 # PHYS_IDX
  19 # Enable OpenOCD ARMv8 core target physical indexing.
  20 # If not specified, defaults to OpenOCD ARMv8 core target logical indexing.
  21 # Syntax: -c "set PHYS_IDX {}"
  22 #
  23 # CHIPNAME
  24 # Specifies the name of the chip.
  25 # Will typically be either qs, qs0, qs1, mq, mq0 or mq1.
  26 # If not specified, defaults to qs.
  27 # Syntax: -c "set CHIPNAME {qs}"
  28 #
  29 # SYSNAME
  30 # Specifies the name of the system.
  31 # Will typically be either qs or mq.
  32 # If not specified, defaults to qs.
  33 # Syntax: -c "set SYSNAME {qs}"
  34 #
  35 # Life-Cycle State (LCS)
  36 # If not specified, defaults to "Secure LCS".
  37 # LCS=0, "Secure LCS"
  38 # LCS=1, "Chip Manufacturing LCS"
  39 # Syntax: -c "set LCS {0}"
  40 # Syntax: -c "set LCS {1}"
  41 #
  42 # CORELIST
  43 # Specify available physical cores by number.
  44 # Example syntax to connect to physical cores 16 and 17.
  45 # Syntax: -c "set CORELIST {16 17}"
  46 #
  47 # COREMASK_LO
  48 # Specify available physical cores 0-63 by mask.
  49 # Example syntax to connect to physical cores 16 and 17.
  50 # Syntax: -c "set COREMASK_LO {0x0000000000030000}"
  51 #
  52 # COREMASK_HI
  53 # Specify available physical cores 64 and above by mask.
  54 # Example syntax to connect to physical cores 94 and 95.
  55 # Syntax: -c "set COREMASK_HI {0x00000000C0000000}"
  56 #
  57 # ARMV8_TAPID
  58 # Can override the ARMV8 TAPID default value if necessary.
  59 # Experimental Use. Most users will not use this option.
  60 # Syntax: -c "set ARMV8_TAPID {0x3BA06477}"
  61 #
  62 # SMPMPRO_TAPID
  63 # Can override the SMPMPRO TAPID default value if necessary.
  64 # Experimental Use. Most users will not use this option.
  65 # Syntax: -c "set SMPMPRO_TAPID {0x4BA00477}"
  66 #
  67 #
  68 # Board File Argument Description
  69 # These optional arguments are defined in the board file and
  70 # referenced by the target file. See the corresponding board
  71 # files for examples of their use.
  72 #
  73 # SMP_STR
  74 # This option is used primarily for a dual socket system and it is not
  75 # recommended for a single socket setup. This option configures whether
  76 # the SMP ARMv8 core grouping is maintained at the board or target cfg level.
  77 # Specify the option if the SMP core grouping is defined at the board level.
  78 # Do not specify if the SMP core grouping is defined at the chip level.
  79 # If not specified, defaults to SMP core grouping defined per socket.
  80 # If specified, "SMP_STR=target smp", the SMP core grouping is maintained
  81 # at the board cfg level.
  82 # Used in conjunction with the SPLITSMP option to group two chips into
  83 # a single SMP configuration or maintain as two separate SMP sessions.
  84 #
  85 # CORE_INDEX_OFFSET
  86 # Specifies the starting logical core index value.
  87 # Used for dual-socket systems.
  88 # For socket #0, set to 0.
  89 # For socket #1, set the starting logical core based from
  90 # the last logical core on socket #0.
  91 # If not specified, defaults to 0.
  92 #
  93
  94 #
  95 # Configure defaults for target.
  96 # Can be overridden in board configuration file.
  97 #
  98
  99 if { [info exists SMP_STR] } {
 100         # SMP configured at the dual socket board level
 101         set _SMP_STR $SMP_STR
 102 } else {
 103         # SMP configured at the single socket target level
 104         set _SMP_STR "target smp"
 105 }
 106
 107 if { [info exists CHIPNAME] } {
 108         set _CHIPNAME $CHIPNAME
 109 } else {
 110         set _CHIPNAME qs
 111 }
 112
 113 if { [info exists SYSNAME] } {
 114         set _SYSNAME $SYSNAME
 115 } else {
 116         set _SYSNAME qs
 117 }
 118
 119 if { [info exists CORE_INDEX_OFFSET] } {
 120         set _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET
 121 } else {
 122         set _CORE_INDEX_OFFSET 0
 123 }
 124
 125 if { [info exists ENDIAN] } {
 126         set _ENDIAN $ENDIAN
 127 } else {
 128         set _ENDIAN little
 129 }
 130
 131 if { [info exists ARMV8_TAPID] } {
 132         set _ARMV8_TAPID $ARMV8_TAPID
 133 } else {
 134         if { [info exists MQ_ENABLE] } {
 135                 # Configure for Mystique
 136                 set _ARMV8_TAPID 0x3BA06477
 137                 set _MAX_CORE 128
 138         } else {
 139                 # Configure for Quicksilver
 140                 set _ARMV8_TAPID 0x2BA06477
 141                 set _MAX_CORE 80
 142         }
 143 }
 144
 145 if { [info exists SMPMPRO_TAPID] } {
 146         set _SMPMPRO_TAPID $SMPMPRO_TAPID
 147 } else {
 148         set _SMPMPRO_TAPID 0x4BA00477
 149 }
 150
 151 if { [info exists CORELIST] } {
 152         set _CORELIST $CORELIST
 153 } else {
 154         if { [info exists COREMASK_LO] } {
 155                 set _COREMASK_LO $COREMASK_LO
 156         } else {
 157                 set _COREMASK_LO 0x0
 158         }
 159
 160         if { [info exists COREMASK_HI] } {
 161                 set _COREMASK_HI $COREMASK_HI
 162         } else {
 163                 set _COREMASK_HI 0x0
 164         }
 165
 166         set _CORELIST {}
 167
 168         set _MASK 0x1
 169         for {set i 0} {$i < 64} {incr i} {
 170                 if { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } {
 171                         set _CORELIST "$_CORELIST $i"
 172                 }
 173                 set _MASK [expr {$_MASK << 0x1}]
 174         }
 175
 176         set _MASK 0x1
 177         for {} {$i < $_MAX_CORE} {incr i} {
 178                 if { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } {
 179                         set _CORELIST "$_CORELIST $i"
 180                 }
 181                 set _MASK [expr {$_MASK << 0x1}]
 182         }
 183 }
 184
 185 #
 186 # Definition of target names
 187 #
 188 set _TARGETNAME_PMPRO pmpro
 189 set _TARGETNAME_SMPRO smpro
 190 set _TARGETNAME_ARMV8 armv8
 191
 192 #
 193 # Configure JTAG TAPs - TAP chain declaration order is important
 194 #
 195
 196 jtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
 197 set _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap
 198
 199 jtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
 200 set _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap
 201
 202 jtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID
 203 set _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap
 204
 205 set _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap
 206 set _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap
 207 set _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap
 208
 209 set _AP_PMPRO_AHB 0
 210 set _AP_SMPRO_AHB 0
 211 set _AP_ARMV8_APB 0x00010000
 212 set _AP_ARMV8_AXI 0x00020000
 213
 214 #
 215 # Configure JTAG DAPs
 216 #
 217
 218 dap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5
 219 dap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5
 220 dap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6
 221
 222 if { [info exists LCS] && [expr {"$LCS"!="0"}] } {
 223         #
 224         # Create the DAP AHB-AP MEM-AP target for the PMPRO CPU
 225         #
 226
 227         target create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
 228
 229         #
 230         # Configure target PMPRO CPU
 231         #
 232
 233         target create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
 234
 235         #
 236         # Create the DAP AHB-AP MEM-AP target for the SMPRO CPU
 237         #
 238
 239         target create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
 240
 241         #
 242         # Configure target SMPRO CPU
 243         #
 244
 245         target create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
 246 }
 247
 248 # Create the DAP APB-AP MEM-AP target for the ARMV8 cores
 249 target create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB
 250
 251 # Create the DAP AXI-AP MEM-AP target for the ARMV8 cores
 252 target create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI
 253
 254 # Set CSW register value default correctly for AXI accessible device memory:
 255 # Select the correct Access Port Number
 256 $_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI
 257 # First set the CSW to OpenOCD's internal default
 258 $_DAPNAME_ARMV8 apcsw default
 259 # Set Domain[1:0]=b'11  (CSW[14:13]=b'11)
 260 # Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000)
 261 # Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'.
 262 # Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access.
 263 $_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000
 264
 265 #
 266 # Configure target CPUs
 267 #
 268
 269 set logical_index $_CORE_INDEX_OFFSET
 270
 271 foreach physical_index $_CORELIST {
 272         if { [info exists PHYS_IDX] } {
 273                 set logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}]
 274         }
 275
 276         # Format a string to reference which CPU target to use
 277         if { [info exists SPLITSMP] } {
 278                 eval "set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index"
 279         } else {
 280                 eval "set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index"
 281         }
 282
 283         # Create and configure Cross Trigger Interface (CTI) - required for halt and resume
 284         set _CTINAME $_TARGETNAME.cti
 285         set _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}]
 286         cti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}]
 287
 288         # Create the target
 289         target create $_TARGETNAME aarch64 -endian $_ENDIAN \
 290                 -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \
 291                 -rtos hwthread -cti $_CTINAME -coreid $logical_index
 292
 293         # Build string used to enable SMP mode for the ARMv8 CPU cores
 294         set _SMP_STR "$_SMP_STR $_TARGETNAME"
 295
 296         # Clear CTI output/input enables that are not configured by OpenOCD for aarch64
 297         $_TARGETNAME configure -event reset-init [subst {
 298                 $_CTINAME write INEN0 0x00000000
 299                 $_CTINAME write INEN1 0x00000000
 300                 $_CTINAME write INEN2 0x00000000
 301                 $_CTINAME write INEN3 0x00000000
 302                 $_CTINAME write INEN4 0x00000000
 303                 $_CTINAME write INEN5 0x00000000
 304                 $_CTINAME write INEN6 0x00000000
 305                 $_CTINAME write INEN7 0x00000000
 306                 $_CTINAME write INEN8 0x00000000
 307
 308                 $_CTINAME write OUTEN0 0x00000000
 309                 $_CTINAME write OUTEN1 0x00000000
 310                 $_CTINAME write OUTEN2 0x00000000
 311                 $_CTINAME write OUTEN3 0x00000000
 312                 $_CTINAME write OUTEN4 0x00000000
 313                 $_CTINAME write OUTEN5 0x00000000
 314                 $_CTINAME write OUTEN6 0x00000000
 315                 $_CTINAME write OUTEN7 0x00000000
 316                 $_CTINAME write OUTEN8 0x00000000
 317         }]
 318
 319         incr logical_index
 320 }
 321
 322 if { [info exists SMP_STR] } {
 323         # Return updated SMP configuration string back to board level
 324         set SMP_STR $_SMP_STR
 325 } else {
 326         # For single socket per SMP configuration, evaluate the string
 327         eval $_SMP_STR
 328 }
 329
 330 if { [info exists CORE_INDEX_OFFSET] } {
 331         # For multi-socket, return total number of cores back to board level
 332         set CORE_INDEX_OFFSET $logical_index
 333 }