tcl/target/at91sam9260_ext_RAM_ext_flash.cfg

   1 ######################################
   2 # Target:    Atmel AT91SAM9260
   3 ######################################
   4
   5 source [find target/at91sam9261.cfg]
   6
   7 reset_config trst_and_srst
   8
   9 adapter_khz 4
  10
  11 adapter_nsrst_delay 200
  12 jtag_ntrst_delay 200
  13
  14 scan_chain
  15 $_TARGETNAME configure -event reset-start {
  16         # at reset chip runs at 32khz
  17         adapter_khz 8
  18 }
  19
  20 $_TARGETNAME configure -event reset-init {at91sam_init}
  21
  22 # Flash configuration
  23 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
  24 set _FLASHNAME $_CHIPNAME.flash
  25 flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
  26
  27 # Faster memory downloads. This is disabled automatically during
  28 # reset init since all reset init sequences are too short for
  29 # fast memory access
  30 arm7_9 dcc_downloads enable
  31 arm7_9 fast_memory_access enable
  32
  33 proc at91sam_init { } {
  34         mww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset
  35         mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
  36
  37         mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
  38         sleep 20                          ;# wait 20 ms
  39         mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
  40         sleep 10                          ;# wait 10 ms
  41         mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
  42         sleep 20                          ;# wait 20 ms
  43         mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler
  44         sleep 10                          ;# wait 10 ms
  45         mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected
  46         sleep 10                          ;# wait 10 ms
  47
  48         # Now run at anything fast... ie: 10mhz!
  49         adapter_khz 10000                    ;# Increase JTAG Speed to 6 MHz
  50
  51         mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
  52         mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0
  53         mww 0xffffec08 0x00160016         ;# SMC_CYCLE0
  54         mww 0xffffec0c 0x00161003         ;# SMC_MODE0
  55
  56         mww 0xfffff870 0xffff0000         ;# PIO_ASR : Select peripheral function for D15..D31
  57         mww 0xfffff804 0xffff0000         ;# PIO_PDR : Disable PIO function for D15..D31
  58
  59         mww 0xffffef1c 0x2                ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
  60
  61         mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  62         #mww 0xffffea08 0x85227254         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
  63
  64         mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
  65         mww 0x20000000 0
  66         mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
  67         mww 0x20000000 0
  68         mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  69         mww 0x20000000 0
  70         mww 0xffffea00 0x4
  71         mww 0x20000000 0
  72         mww 0xffffea00 0x4
  73         mww 0x20000000 0
  74         mww 0xffffea00 0x4
  75         mww 0x20000000 0
  76         mww 0xffffea00 0x4
  77         mww 0x20000000 0
  78         mww 0xffffea00 0x4
  79         mww 0x20000000 0
  80         mww 0xffffea00 0x4
  81         mww 0x20000000 0
  82         mww 0xffffea00 0x4
  83         mww 0x20000000 0
  84         mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
  85         mww 0x20000000 0
  86         mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
  87         mww 0x20000000 0
  88         mww 0xffffea04 0x5d2              ;# SDRAMC_TR : Set refresh timer count to 15us
  89 }