tcl/target/at91samdXX.cfg

   1 #
   2 # script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
   3 #
   4
   5 #
   6 # samdXX devices only support SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9
  10 if { [info exists CHIPNAME] } {
  11    set _CHIPNAME $CHIPNAME
  12 } else {
  13    set _CHIPNAME at91samd
  14 }
  15
  16 if { [info exists ENDIAN] } {
  17    set _ENDIAN $ENDIAN
  18 } else {
  19    set _ENDIAN little
  20 }
  21
  22 # Work-area is a space in RAM used for flash programming
  23 # By default use 2kB
  24 if { [info exists WORKAREASIZE] } {
  25    set _WORKAREASIZE $WORKAREASIZE
  26 } else {
  27    set _WORKAREASIZE 0x800
  28 }
  29
  30 if { [info exists CPUTAPID] } {
  31    set _CPUTAPID $CPUTAPID
  32 } else {
  33    set _CPUTAPID 0x4ba00477
  34 }
  35
  36 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  37 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  38
  39 set _TARGETNAME $_CHIPNAME.cpu
  40 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  41
  42 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  43
  44 # SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
  45 # deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
  46 #
  47 # dsu_reset_deassert configures whether we want to run or halt out of reset,
  48 # then instruct the DSU to let us out of reset.
  49 $_TARGETNAME configure -event reset-deassert-post {
  50         at91samd dsu_reset_deassert
  51 }
  52
  53 # SRST (wired to RESET_N) resets debug circuitry
  54 # srst_pulls_trst is not configured here to avoid an error raised in reset halt
  55 reset_config srst_gates_jtag
  56
  57 # Do not use a reset button with other SWD adapter than Atmel's EDBG.
  58 # DSU usually locks MCU in reset state until you issue a reset command
  59 # in OpenOCD.
  60
  61 # SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
  62 # Other members of family usually use SYSCLK = 4 MHz after reset.
  63 # Datasheet does not specify SYSCLK to SWD clock ratio.
  64 # Usually used SYSCLK/6 is slow, testing shows that debugging can
  65 # work @ SYSCLK/2 but your mileage may vary.
  66 # This limit is most probably imposed by incorrectly handled SWD WAIT
  67 # on some SWD adapters.
  68
  69 adapter_khz 400
  70
  71 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
  72 # without problem at maximal clock speed. Atmel recommends
  73 # adapter speed less than 10 * CPU clock.
  74 # adapter_khz 5000
  75
  76 if {![using_hla]} {
  77    # if srst is not fitted use SYSRESETREQ to
  78    # perform a soft reset
  79    cortex_m reset_config sysresetreq
  80 }
  81
  82 set _FLASHNAME $_CHIPNAME.flash
  83 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME